RS Decoder Erasure Control Using Symbol Reliability Tracking

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Solution Overview

Problem

Current memory systems face inefficiencies in error correction, particularly in distinguishing symbol reliability levels during the Reed-Solomon decoding process, which affects the accuracy and efficiency of error correction operations.

Innovation Solution

Incorporating a Reed-Solomon (RS) decoder, a reliability tracking circuit, and an erasure control circuit to generate and store reliability information, allowing symbols to be erased based on reliability levels from low to high, enabling an erasure-based soft-decision decoding operation to improve error correction efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional ECC decoding is used without reliability tracking, then the decoding process is simpler and faster, but the error correction accuracy is lower because all symbols are treated equally

Engineering Contradiction:
Improveerror correction accuracyVSAvoiddecoding system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the decoding process into multiple stages: initial ECC decoding, reliability tracking, erasure control, and iterative re-decoding. Symbols are segmented by reliability levels (high, medium, low) and processed differently in each iteration, allowing accurate error correction while managing complexity through structured segmentation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The reliability tracking circuit performs preliminary analysis of symbol reliability before the main error correction process. By pre-classifying symbols into reliability categories and preparing erasure control information in advance, the system enables more accurate error correction in subsequent decoding iterations without adding excessive complexity to the core decoding logic.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If reliability tracking and erasure control are implemented, then error correction efficiency is improved through iterative decoding, but the processing time and computational load increase

Engineering Contradiction:
Improveerror correction efficiencyVSAvoiddecoding processing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements periodic iterative decoding where the RS decoder repeatedly processes data through multiple cycles. In each iteration, reliability tracking updates symbol confidence levels, erasure control adjusts which symbols are targeted, and the decoder re-attempts correction. This periodic refinement continues until errors are corrected or maximum iterations are reached, improving efficiency by focusing computational effort on the most likely error sources in each cycle.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11108412B2Memory systems and methods of correcting errors in the memory systems
Publication Date: 2021.08.31 MIMIRIP LLC
  • US11108412B2 patent drawing
  • US11108412B2 patent drawing
  • US11108412B2 patent drawing

AI summary

A memory system includes a Reed-Solomon (RS) decoder, a reliability tracking circuit, and an erasure control circuit. The RS decoder performs an error correction decoding operation of ‘K’-number of symbols outputted from a memory medium. The reliability tracking circuit generates and stores information on a reliability of the symbols, error occurrence possibilities of which are distinguished into a plurality of different levels according to the error correction decoding operation performed by the RS decoder. The erasure control circuit controls the RS decoder such that the symbols are erased in order of the reliability of the symbols from a low reliable symbol to a high reliable symbol and the error correction decoding operation is performed according to the information on the reliability of the symbols stored in the reliability tracking circuit.