Reed-Solomon Decoder Parallelism for Low-Latency Error Correction

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Solution Overview

Problem

Current error correction mechanisms, such as Forward Error Correction (FEC) schemes, increase latency in data decoding as the number of errors to be corrected increases, leading to potential system failures and delays in data transmission.

Innovation Solution

A low latency decoder that employs a Reed-Solomon (RS) decoding scheme to correct two or more symbols per clock cycle by determining error locations and magnitudes in parallel, reducing decoding latency and mitigating system delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional error correction decoding is used to correct multiple errors, then error correction capability is improved, but decoding latency increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoiddecoding latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The decoding process is divided into independent parallel stages: error location determination and error magnitude determination operate separately and simultaneously. Each stage processes different aspects of the decoding problem independently, allowing them to execute in parallel without interfering with each other, thus reducing overall decoding latency while maintaining full error correction capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from sequential processing (single dimension in time) to parallel processing (adding a spatial dimension by operating on multiple data paths simultaneously). By determining error locations and error magnitudes through separate parallel computational paths rather than sequential steps, the system achieves both high error correction capability and low latency.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the number of errors to be corrected is increased, then error correction capability is improved, but system latency increases beyond acceptable parameters

Engineering Contradiction:

Improvenumber of errors correctedVSAvoidsystem latency

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The parallel architecture enables continuous error correction processing without idle waiting periods. While traditional sequential decoding must complete one stage before starting the next, this implementation maintains continuous useful action by having error location and error magnitude determination proceed simultaneously, maximizing throughput and minimizing system latency even when correcting multiple errors.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11651830B2Low latency decoder for error correcting codes

Publication Date: 2023.05.16 SYNOPSYS INC

AI summary

A method for error correction comprises receiving data at a first device, and decoding, by decoder circuitry of the first device, the data. Decoding the data comprises determining a first error location within the data, and determining a first error magnitude within the data in parallel with determining the first error location. Decoding the data further comprises performing error correction to generate the decoded data based on the first error location and the first error magnitude. The method further comprises transmitting the decoded data to a second device.