RS-FEC Error Emulation for Accurate Post-FEC BER Prediction
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Solution Overview
Problem
Conventional Bit Error Rate Testers (BERTs) struggle to accurately predict the post-FEC Bit Error Ratio (BER) for new Ethernet standards using GF10 Reed-Solomon FEC codes, as they rely on pseudo-random binary sequences and do not support the generation of FEC encoded data, leading to difficulties in error correction.
Innovation Solution
The development of an emulator that groups errors into Reed-Solomon FEC symbols and codewords to determine correctable errors, providing a more accurate representation of the post-FEC BER by emulating the error correction capabilities of FEC codes, which can be used standalone or in conjunction with BERTs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional BERTs use PRBS patterns for error detection, then the equipment complexity is reduced and ease of operation is improved, but the measurement precision of post-FEC BER prediction deteriorates because PRBS-based BERTs cannot accurately represent the error distribution characteristics required by GF10 Reed-Solomon FEC codes
Solution Approach 1:
The patent creates a virtual copy of the GF10 Reed-Solomon FEC error correction process within the BERT device. Instead of requiring actual FEC encoding hardware, the system copies the essential error correction logic and applies it to PRBS patterns, enabling accurate post-FEC BER prediction without adding complex FEC generation hardware
Solution Approach 2:
The patent introduces an intermediary FEC emulation module that sits between the PRBS pattern generator and the error analysis function. This intermediary component translates PRBS error patterns into equivalent FEC codeword error scenarios, allowing the simple PRBS generator to effectively test FEC performance without direct FEC encoding hardware
2Reliability
If BERTs only produce and count errors for PRBS patterns, then the ease of operation is maintained, but the reliability of error correction assessment deteriorates because the error distribution characteristics of actual FEC encoded data cannot be captured
Solution Approach 1:
The patent changes the parameter representation of errors by mapping PRBS bit error positions to FEC symbol and codeword error patterns. Instead of counting raw bit errors in PRBS sequences, the system transforms these into equivalent FEC error scenarios by applying the FEC encoding parameters (GF10 Reed-Solomon code structure, symbol grouping, codeword organization) to the PRBS error data, thereby assessing error correction reliability without changing the operational simplicity of PRBS generation
Data Source
AI summary
Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).