R-S Latch Relaxation Oscillator With Reduced Logic Delay
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Solution Overview
Problem
Conventional relaxation oscillators face limitations in increasing operational frequency due to internal circuit delays, leading to higher current consumption and reduced frequency adjustment range.
Innovation Solution
The proposed relaxation oscillator incorporates an R-S flip-flop coupled with first and second delay circuits, each comprising charging, discharging devices, and comparing/detecting circuits, which reduce logic delay by immediate voltage changes and optimized capacitor discharge, enhancing operational frequency and reducing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional relaxation oscillator circuit is used, then circuit structure is simple, but operational frequency is limited due to internal circuit delays
Solution Approach 1:
The patent extracts and removes the delay-causing elements from the conventional relaxation oscillator circuit. By eliminating the R-S flip-flop and associated delay circuits, the design achieves immediate voltage changes and reduces logic delay, thereby increasing operational frequency without being constrained by internal circuit delays.
Solution Approach 2:
The patent implements immediate voltage changes and optimized capacitor discharge mechanisms that skip through the traditional delayed transition phases. The charging and discharging devices are configured to rapidly transition voltage levels without the gradual delays inherent in conventional designs, effectively rushing through the delay period to achieve higher operational frequencies.
2Speed
If conventional relaxation oscillator circuit is used, then circuit structure is simple, but current consumption increases at higher frequencies
Solution Approach 1:
The patent removes the delay circuits and R-S flip-flop that cause increased current consumption at higher frequencies. By extracting these energy-consuming elements, the oscillator can operate at higher frequencies without the proportional increase in current consumption that plagues conventional designs.
Solution Approach 2:
The oscillator circuit is designed to automatically regulate its operation without requiring additional control circuits or feedback mechanisms that would increase power consumption. The charging and discharging devices self-regulate the capacitor voltage, eliminating the need for extra energy-consuming control elements.
3Adaptability or versatility
If conventional relaxation oscillator circuit is used, then frequency adjustment range is limited, but circuit design is straightforward
Solution Approach 1:
The patent implements a dynamic frequency adjustment mechanism where the oscillation frequency can be continuously varied by changing the charging current or capacitor value. The circuit responds dynamically to parameter changes, enabling wide frequency adjustment range from low to high frequencies without requiring multiple discrete circuit configurations.
Solution Approach 2:
The oscillator frequency is controlled by varying key circuit parameters such as charging current, capacitor capacitance, or resistance values. By changing these parameters, the frequency adjustment range is significantly expanded while maintaining a relatively simple circuit topology based on capacitive charging and discharging cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a faster clock frequency and lower current consumption while maintaining high stability and linearity, making it easier for circuit designers to implement and use.
Implementation Method 1
a first capacitor, and a first discharging device... The first terminal of the first capacitor is coupled to the second terminal of the first charging circuit
Implementation Method 2
When the voltage of the input terminal of the first comparing/detecting circuit is lower than the first voltage, the output terminal of the first comparing/detecting circuit outputs a first logic pulse
Data Source
AI summary
A relaxation oscillator is provided in the present invention. The relaxation oscillator includes a R-S latch, a first delay circuit and a second delay circuit. The input terminal of the first delay circuit is coupled to the Q output terminal of the R-S latch, and the output terminal of the first delay circuit is coupled to the reset terminal of the R-S latch. The input terminal of the second delay circuit is coupled to the inversion Q output terminal of the R-S latch, and the output terminal of the second delay circuit is coupled to the set terminal of the R-S latch. When the input terminal of the first delay circuit inputs a first logic voltage, after a delay time, the output terminal of the first delay circuit outputs a second logic pulse. When the input terminal of the second delay circuit inputs the first logic voltage, after the delay time, the output terminal of the second delay circuit outputs the second logic pulse.