RS Syndrome Circuit for Out-of-Order Symbol Processing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing methods for calculating syndromes in Reed-Solomon error correction codes are inefficient, especially when symbols are received out of order, and they do not effectively support on-the-fly syndrome calculation in generalized concatenated error correction codes.

Innovation Solution

A hardware circuit is designed to calculate syndromes in Reed-Solomon error correction codes, utilizing multiplexors and multipliers to efficiently process symbols out of order and maintain Reed-Solomon syndrome (RSS) for decoding between activations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional syndrome calculation methods are used, then the calculation can be performed, but the efficiency is low especially when symbols are received out of order

Engineering Contradiction:
Improvesyndrome calculation efficiencyVSAvoidhardware circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The syndrome calculation is divided into p parallel groups, each handled by a separate multiplexor and multiplier unit. This segmentation allows simultaneous processing of multiple symbols and reduces the sequential calculation burden, significantly improving efficiency when symbols arrive out of order.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The hardware circuit is designed to handle multiple functions: it can process symbols in any order, maintain running syndrome values between activations, and calculate multiple syndromes simultaneously. The multiplexors and multipliers are configured to universally handle different symbol positions and syndrome calculations without requiring separate dedicated circuits for each case.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If on-the-fly syndrome calculation is implemented, then decoding efficiency improves, but hardware resources increase

Engineering Contradiction:
Improvedecoding efficiencyVSAvoidhardware resources
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The circuit merges multiple calculation functions into a unified hardware structure. The same p multiplexors and p multipliers are used to calculate all p syndromes simultaneously by processing symbols through shared computational paths, reducing the total hardware required compared to having separate calculation units for each syndrome.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The circuit performs preliminary calculations by maintaining running syndrome values between activations. As symbols are received, the circuit continuously updates syndrome values in preparation for decoding, so that when decoding is needed, the calculations are already complete or near-complete, eliminating the need for intensive real-time computation during decoding operations.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If delta-syndromes are stored, then syndrome information is preserved, but storage overhead increases

Engineering Contradiction:
Improvesyndrome information preservationVSAvoidstorage overhead
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The circuit extracts and maintains only the essential syndrome information needed for decoding by continuously updating running syndrome values. Instead of storing all intermediate delta-syndromes, the circuit extracts the cumulative syndrome values that are sufficient for error correction, significantly reducing storage requirements while preserving all necessary decoding information.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250199768A1Hardware efficient out-of-order syndrome calculation
Publication Date: 2025.06.19 SAMSUNG ELECTRONICS CO LTD
  • US20250199768A1 patent drawing
  • US20250199768A1 patent drawing
  • US20250199768A1 patent drawing

AI summary

A hardware circuit for calculating syndromes in Reed-Solomon (RS) error correction codes comprises a plurality of p multiplexors, where p is a positive integer, where each multiplexor receives α{circumflex over ( )}i powers that are selected by j, wherein α is a primitive point of a RS generator polynomial and j is an index of an RS symbol, where i and j are positive integers, where 1≤i≤p, and outputs α{circumflex over ( )}(i×j); and a plurality of p first multipliers, where each first multiplier is associated with a multiplexor and receives α{circumflex over ( )}(i×j) from the associated multiplexor, multiplies the α{circumflex over ( )}(i×j) by a jth RS-word symbol Rj and outputs Rj×α{circumflex over ( )}(i×j). The hardware circuit calculates and outputs p products of the form Rj×α{circumflex over ( )}(i×j), wherein 1≤i≤p.