Receive-Side Scaling via Sub-Queue Segmentation on Multi-Core Processors

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current solutions for processing high bit rate data in computer networks, such as Receive Side Scaling (RSS), Network Processing Units (NPUs), dedicated hardware or software load balancers, and embedded switching/routing devices, are either expensive, limited in scalability, or introduce bottlenecks, failing to provide a cost-effective and easily scalable method.

Innovation Solution

A system utilizing a multi-core processor with a circular queue divided into sub-queues, where each sub-queue is assigned to a processing core, allowing for efficient distribution and processing of incoming data streams, leveraging general purpose processors to handle high bit rates without the need for specialized hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single processor is used to receive data at high bit rates, then the system is simpler and costs less, but the processor cannot process the volume of data as it arrives, forming a bottleneck

Engineering Contradiction:

Improvedata processing capacityVSAvoidprocessor architecture

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the circular queue into multiple sub-queues, with each sub-queue assigned to a specific processing core. This segmentation allows multiple cores to process data simultaneously, increasing overall data processing capacity while maintaining a relatively simple system architecture based on general-purpose processors.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If Receive Side Scaling (RSS) is implemented in NIC hardware, then data distribution is automated, but the solution is limited to NIC capabilities and fails with certain packet types

Engineering Contradiction:

Improvepacket handling capabilityVSAvoidhardware requirements

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent replaces hardware-based RSS functionality with a software implementation on general-purpose multi-core processors. The circular queue with sub-queues and associated software logic provides adaptive packet handling for various packet types, tunneling, and fragmentation without requiring specialized NIC hardware, thus improving versatility while reducing hardware complexity.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If Network Processing Units (NPUs) with specialized packet scheduling hardware are used, then packet scheduling is efficient, but the cost is significantly higher and scalability is limited

Engineering Contradiction:

Improvepacket processing efficiencyVSAvoidsystem cost

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The patent uses general-purpose multi-core processors that can handle multiple functions including packet reception, processing, and scheduling. The circular queue mechanism with sub-queues provides efficient packet distribution without requiring specialized NPU hardware, thereby reducing system cost while maintaining high packet processing efficiency and scalability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Adaptability or versatility

If dedicated hardware or software load balancers are used, then traffic distribution is scalable, but a choke point is introduced in the system reducing reliability

Engineering Contradiction:

Improvetraffic distribution flexibilityVSAvoidsystem reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the data reception and processing function across multiple processing cores, eliminating the single-point bottleneck inherent in dedicated load balancers. Each core independently processes packets from its assigned sub-queue, providing both scalability and improved reliability through distributed processing without a central choke point.

Inventive Principle:

Principle #1Segmentation

5Productivity

If embedded switching/routing devices are used in the NIC, then parsing and hashing functionality is integrated, but cost and complexity increase

Engineering Contradiction:

Improvepacket handling functionalityVSAvoidNIC architecture

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the packet parsing, hashing, and scheduling functionality from the NIC hardware and implements it in software on general-purpose multi-core processors. This extraction eliminates the need for complex embedded switching/routing devices in the NIC, reducing both cost and device complexity while maintaining full packet handling functionality through the software-based circular queue mechanism.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS9639403B2Receive-side scaling in a computer system using sub-queues assigned to processing cores

Publication Date: 2017.05.02 RIBBON COMMUNICATIONS OPERATING CO INC

AI summary

A system, method, and computer program product are provided for receiving an incoming data stream. The system comprises a multi-core processor with a memory unit that is configured to include a circular queue that receives a data stream. The circular queue is divided into a plurality of sub-queues determined as a multiple of the number of processing cores, and each sub-queue is assigned to one processing core such that as data is received into a region covered by a particular sub-queue, the processing core assigned to the particular sub-queue processes the data. The system is also configured to update a head pointer and a tail pointer of the circular queue. The head pointer is updated as data is received into the circular queue and the tail pointer is updated by a particular processing core as it processes data in its assigned sub-queue.