RTC Fixed-Point Coding for Carry-Free Parallel ALU Circuits
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Solution Overview
Problem
Modern parallel processing chips face challenges in supporting carry-calculation due to dependencies on carry bit computing, leading to complexity in arithmetic-logic unit (ALU) circuitry design and limiting the parallelization degree and computation units in GPUs, CPUs, TPUs, NPUs, and other computing devices.
Innovation Solution
Implementing a redundancy-tolerated symmetric binary coding (RTC) method for fixed-point number coding in ALU circuitry, ensuring each integer has a unique representation and allowing constant-time verification, simplifying carry bit computation, and enabling simpler CMOS circuit designs for faster parallel computing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional binary coding is used for carry-calculation, then arithmetic operations can be performed, but the ALU circuitry design becomes complex and parallelization degree is limited
Solution Approach 1:
The patent segments the addition operation into independent bit-position operations using redundant number system representation. Each bit position can be processed independently without carry propagation to adjacent positions, enabling parallel processing of multiple bit positions simultaneously. This segmentation eliminates the sequential dependency inherent in traditional binary addition.
Solution Approach 2:
The patent changes the parameter representation from standard binary to a redundant number system where each digit can take multiple values (e.g., -1, 0, 1). This parameter change allows the sum of two digits at any position to remain within a manageable range, eliminating the need for carry calculation and simplifying the ALU circuitry while enabling higher parallelization.
2Measurement precision
If carry bit computing is implemented, then accurate addition can be achieved, but the computation time increases and constant-time operation is not achieved
Solution Approach 1:
The addition operation is segmented into independent bit-position operations where each position can be processed simultaneously. The redundant number system representation ensures that the sum at each position can be determined independently without waiting for carry bits from previous positions, achieving constant-time addition regardless of the number of bits.
3Productivity
If more computation units are added to increase parallel processing capability, then productivity improves, but device complexity and area increase
Solution Approach 1:
The patent enables segmentation of computation into independent bit-position operations that can be processed in parallel. This allows the same ALU unit to handle multiple bit positions simultaneously through parallel processing, effectively increasing computation units without physically adding more hardware components, thus improving productivity without proportionally increasing chip area.
Data Source
AI summary
A code method, a computer program product, and a system, for implementing a code method of Redundancy-Tolerated symmetric binary Coding (RTC) for massive parallel ALU circuitry design in GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Processing Unit), Artificial Intelligence Inference Chip, CPU, and other computing chips and devices. The method can remove redundancy and reduce the dependency on carry bit computing. RTC code method can provide a redundancy-tolerated digital coding method for negative and positive integers, and can guarantee that number “0” have one and only one representation.