Real-Time Clock Phase Feedback for Aging Frequency Drift
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Solution Overview
Problem
Real-time clock devices face challenges in maintaining high accuracy due to frequency errors caused by aging, which require frequent updates and are difficult to correct without increasing device size and power consumption.
Innovation Solution
A real-time clock device that includes an interface circuit, oscillation circuit, frequency division circuit, time counter, phase comparator, and processing circuit, which updates internal time based on timestamp information and adjusts oscillation frequency to minimize phase and time differences between the reference signal and the frequency-divided clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If time information is updated frequently to maintain high accuracy, then timekeeping accuracy is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent implements a feedback mechanism where the phase difference between the reference signal and frequency-divided clock signal is continuously measured by a phase comparator. This phase difference information is fed back to the processing circuit, which then adjusts the oscillation frequency of the oscillation circuit to minimize the phase difference, thereby maintaining high timekeeping accuracy without requiring frequent updates of time information.
Solution Approach 2:
The patent replaces the conventional mechanical time-counting system with a phase-based feedback control system. Instead of relying solely on time counter updates, the system uses phase comparison and frequency adjustment mechanisms to maintain accuracy, reducing the need for frequent time information updates and simplifying the overall device structure.
2Measurement precision
If time information is updated frequently to maintain high accuracy, then timekeeping accuracy is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic phase comparison and frequency adjustment actions instead of continuous time information updates. The phase comparator periodically measures the phase difference, and the processing circuit periodically adjusts the oscillation frequency based on this measurement, reducing power consumption while maintaining high timekeeping accuracy.
Solution Approach 2:
The feedback mechanism allows the system to maintain accuracy by making small, periodic frequency adjustments based on phase difference measurements, rather than requiring frequent complete time information updates. This significantly reduces power consumption while preserving timekeeping precision.
3Device complexity
If conventional time-counting methods are used, then device structure is simple, but frequency errors accumulate due to aging
Solution Approach 1:
The patent introduces a feedback control loop that continuously monitors the phase difference between the reference signal and the frequency-divided clock signal. The processing circuit uses this feedback to dynamically adjust the oscillation frequency, compensating for frequency errors caused by aging and other factors, thereby maintaining high reliability without significantly increasing device complexity.
Solution Approach 2:
The system implements self-service through automatic frequency adjustment. The phase comparator and processing circuit work together to automatically detect and correct frequency deviations caused by aging, eliminating the need for external calibration or manual intervention while maintaining frequency accuracy.
Data Source
AI summary
A real-time clock device includes: an interface circuit that receives timestamp information; an oscillation circuit that outputs an oscillation clock signal; a frequency division circuit that divides a frequency of the oscillation clock signal to generate a frequency-divided clock signal; a time counter that generates information regarding an internal time based on the frequency-divided clock signal; a phase comparator that compares phases of a reference signal and the frequency-divided clock signal and calculates a phase difference; and a processing circuit that performs processing of updating the information regarding the internal time of the time counter based on an input time indicated by the input timestamp information, and adjusts a frequency of the oscillation circuit based on a time difference between the input time and the internal time and the phase difference.