Synchronous RTC Prescaler Calibration for Frequency Offset Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional real-time clock (RTC) circuits face challenges in accurately maintaining time and calendar data due to frequency offset variations, leading to significant errors over time, and require complex manual testing processes that increase manufacturing costs and reduce throughput.
Innovation Solution
A fully synchronous real-time clock prescaler design that compensates for frequency offset by loading corrected counter values without clock manipulation, enabling compatibility with modern circuit synthesis and test tools, and allowing for automatic test pattern generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RTC circuits use manual testing processes to verify frequency offset correction, then testing coverage can be achieved, but manufacturing costs increase and throughput decreases
Solution Approach 1:
The RTC circuit performs self-testing through automatic test pattern generation (ATPG) by providing test mode control signals that enable the circuit to verify its own frequency offset correction functionality without external manual intervention, thereby maintaining reliability while improving manufacturing throughput
Solution Approach 2:
The circuit incorporates preliminary test mode configuration that prepares the RTC for automatic testing during manufacturing by pre-configuring test control signals and patterns, allowing comprehensive testing to be performed automatically without manual setup during production
2Measurement precision
If conventional RTC circuits use clock manipulation methods to correct frequency offset, then frequency accuracy can be improved, but device complexity increases and compatibility with modern synthesis tools is reduced
Solution Approach 1:
The patent replaces mechanical clock manipulation methods with a digital correction approach using a correction counter that calculates and applies frequency offset corrections through digital counting and state loading, thereby maintaining frequency accuracy while reducing circuit complexity and improving compatibility with modern synthesis tools
Solution Approach 2:
The circuit changes the approach from manipulating clock signal timing to modifying the counter state parameters directly, using a correction value loaded into the counter to adjust the frequency output, which simplifies the circuit architecture while maintaining precision
3Device complexity
If RTC circuits do not implement frequency offset correction, then device complexity is reduced, but timekeeping accuracy deteriorates significantly over time
Solution Approach 1:
The frequency offset correction function is segmented into a separate correction counter module that operates independently from the main RTC counter, allowing the correction mechanism to be added without significantly increasing the complexity of the core timekeeping circuit while maintaining accuracy
Data Source
AI summary
In described examples, an apparatus includes: a counter configured to receive a reference clock signal and having a next state input and a current state output; a multiplexer coupled to the next state input of the counter, configured to output one of an incremented next state value and a corrected next state count value responsive to a count correction select control signal; a seconds reference circuit coupled to the current state output of the counter, configured to output a seconds reference signal; an incrementer coupled to the current state output of the counter, configured to output the incremented next state value; and a calibration compensation circuit coupled to a compensate up down input signal and to the current state output of the counter, configured to output the corrected next state count value and the count correction select control signal.