RTL Circuit Malfunction Detection via Formal Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for detecting circuit malfunctions in the register transfer level (RTL) design stage are inefficient, relying on simulation and lint checks that fail to detect all errors, leading to resource wastage and high redesign costs due to their limitations in capturing complete circuit behavior and syntax-based limitations.
Innovation Solution
A method involving signal point extraction from circuit models, generation of property lists for formal verification, and determination of circuit malfunctions using a device with a register extracting unit, property verification generating unit, formal calculation unit, and circuit malfunction determination unit to identify and correct malfunctions through rigorous mathematical proof.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If simulation and lint check methods are used to detect circuit malfunctions, then the detection process is simple and easy to implement, but the detection reliability and completeness are insufficient
Solution Approach 1:
The invention segments the detection process into multiple specialized units: register extracting unit for identifying register signal points, property verification generating unit for creating verification properties, formal calculation unit for executing formal verification, and circuit malfunction determination unit for analyzing results. This segmentation allows each unit to specialize in a specific aspect of verification, improving overall detection reliability while maintaining operational clarity through defined responsibilities.
Solution Approach 2:
The invention introduces an intermediary formal verification system that acts as a bridge between the RTL design and final validation. The formal calculation unit performs mathematical proof-based verification as an intermediary step, generating comprehensive circuit behavior information that mediates between simple simulation and complex manual verification, thereby improving detection reliability without excessive complexity.
2Reliability
If formal verification is used to obtain complete circuit behavior, then the detection reliability is improved, but the device complexity and resource requirements increase
Solution Approach 1:
The verification system is segmented into four functional units that can operate independently and in sequence. This segmentation reduces the perceived complexity by breaking down the formal verification process into manageable stages: extraction, property generation, calculation, and determination. Each unit handles a specific aspect, making the overall complex process more controllable and maintainable.
Solution Approach 2:
The register extracting unit performs preliminary action by identifying and extracting all register signal points before the formal verification process begins. This preliminary extraction creates a structured foundation that simplifies subsequent property generation and verification steps, reducing the complexity burden during the actual formal calculation phase.
3Productivity
If circuit malfunctions are detected late in the design process, then the design can proceed with current resources, but redesign time and costs increase significantly
Solution Approach 1:
The invention performs preliminary circuit malfunction detection during the RTL design stage itself, before implementation and testing phases. By extracting register signal points and performing formal verification at this early stage, potential malfunctions are identified when redesign is least costly and most efficient, preventing time loss that would occur if errors were detected later in the design flow.
Solution Approach 2:
The verification system provides self-service by automatically extracting register information, generating verification properties, and determining malfunctions without requiring extensive manual intervention. This automation enables early detection to occur efficiently during the design stage, improving productivity while minimizing the time penalty that would otherwise be incurred through later redesign efforts.
4Measurement precision
If comprehensive property verification is performed on all signal points, then the detection precision is improved, but the verification time and computational resources increase
Solution Approach 1:
The invention applies local quality by focusing verification efforts specifically on register signal points, which are identified as critical locations for potential malfunctions. Rather than uniformly verifying all circuit signals, the system concentrates computational resources on extracting and verifying properties of register-related signals, thereby improving detection precision for critical areas while managing overall verification time through selective focus.
Solution Approach 2:
The system performs partial verification by concentrating on the most critical signal points (register signals) rather than attempting to verify every possible circuit signal. This partial action approach achieves sufficient detection precision for the most error-prone areas without incurring the excessive time and computational costs that would result from comprehensive verification of the entire circuit.
Data Source
AI summary
A method of detecting a circuit malfunction in a register transfer level, RTL, design stage is disclosed. The method comprises obtaining signal points of each register from a circuit model based on the RTL design stage, generating a property list according to the signal points of each register, wherein the property list includes a property to be verified for each signal point, performing a formal verification operation according to the circuit model and the property list, to determine whether the property of the property list for each signal point in the circuit model is true, and generating a circuit malfunction result according to the signal point whose property is not true.