RTL Circuit Synthesis With Floorplan Simulation for PPA Optimization
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Solution Overview
Problem
Designing application-specific integrated circuits (ASIC) and System on Chips (SoC) with semiconductor devices is labor-intensive and time-consuming, particularly in optimizing power-performance-area characteristics across various silicon design technologies.
Innovation Solution
A method and system for optimizing circuit synthesis by importing register transfer level code, converting it into structurally defined circuit designs, generating floor plans, simulating physically, and sweeping over a range of operating conditions to analyze power, performance, and area characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual optimization techniques are used for circuit design, then design precision can be achieved, but development time and labor intensity increase significantly
Solution Approach 1:
The system enables self-service optimization by automatically importing register transfer level code, converting it to structurally defined circuit designs, generating floor plans, and performing physical simulations with operating condition sweeps. The automated synthesis process eliminates manual labor while maintaining optimization precision through systematic analysis of power, performance, and area characteristics across multiple device technologies.
Solution Approach 2:
The patent replaces manual mechanical design processes with automated computational systems. The synthesis toolchain substitutes human engineers' manual optimization work with algorithm-driven processes that automatically convert behavioral code descriptions into optimized structural circuit designs, floor plans, and implementation specifications across various semiconductor technology nodes.
2Manufacturing precision
If comprehensive optimization analysis is performed across multiple operating conditions, then optimal power-performance-area characteristics are achieved, but computational complexity and processing time increase
Solution Approach 1:
The optimization process is segmented into distinct automated stages: importing register transfer level code, converting to structurally defined circuit designs, generating floor plans, creating physically simulated circuits, and sweeping operating conditions. Each stage processes specific aspects of the design independently, managing computational complexity through systematic division of the synthesis workflow while achieving comprehensive power-performance-area optimization.
3Productivity
If automated synthesis tools are used, then productivity increases, but design precision and control may be reduced
Solution Approach 1:
The automated synthesis system incorporates feedback mechanisms by performing physical simulations of generated circuits and sweeping through ranges of operating conditions to analyze power, performance, and area characteristics. This feedback loop validates design accuracy and enables iterative optimization, ensuring that automated productivity gains do not compromise design precision while systematically exploring design space across multiple semiconductor technology nodes.
Data Source
AI summary
Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.