RTL Compilation Advisor for Emulator Model Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Designers face challenges in selecting optimal compilation parameter values for converting register transfer level (RTL) circuit designs into emulator models, particularly due to varying timing and size sensitivity across different circuit design portions, which can lead to inefficient or incorrect emulation.
Innovation Solution
A compilation tool and advisor analyze the circuit design to identify critical paths and hierarchical modules, selecting appropriate compilation parameter values, such as retiming techniques and memory mapping, to improve operational delay and capacity requirements, while considering mutual exclusivity and hierarchical boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single combination of compilation parameter values is used to compile different circuit design portions, then the compilation process is simplified, but the operational speed and resource usage cannot be optimized for portions with varying timing and size sensitivity
Solution Approach 1:
The patent applies local quality by assigning different compilation parameter values to different hierarchical modules based on their specific characteristics. The system analyzes each module's timing sensitivity and size requirements, then selects appropriate compilation parameters for each module individually rather than using a uniform approach across the entire design. This enables optimization of operational speed for timing-critical modules while managing resource usage for other modules.
2Speed
If compilation parameters are optimized for timing-critical portions, then operational delay is reduced, but resource usage increases
Solution Approach 1:
The patent employs parameter changes by systematically varying compilation parameter values based on the timing and size sensitivity characteristics of different circuit portions. The system adjusts parameters such as optimization levels, resource allocation settings, and compilation strategies to achieve the desired balance between operational delay and resource usage for each specific module.
3Productivity
If multiple compilation parameter combinations are used for different circuit portions, then optimization is improved, but the complexity of selecting and managing parameters increases
Solution Approach 1:
The patent implements self-service by enabling the compilation system to automatically analyze hierarchical modules, identify their timing and size sensitivity characteristics, and select appropriate compilation parameter values without requiring manual intervention. The system performs self-analysis and self-optimization, reducing the complexity of parameter management while maintaining high optimization quality.
4Adaptability or versatility
If hierarchical boundaries are respected during compilation, then module reusability is maintained, but cross-module optimization opportunities are lost
Solution Approach 1:
The patent applies segmentation by dividing the circuit design into hierarchical modules that can be independently analyzed and compiled. The system processes each module separately while maintaining the ability to consider cross-module relationships during parameter selection, thus preserving module reusability while enabling cross-module optimization where beneficial.
Data Source
AI summary
Techniques and tool for selecting compilation parameter values for compiling a first description of a circuit design, such as a register transfer language description, into a second description of the circuit design, such as a model description for implementation with an emulator are provided. According to various examples of the invention, a compilation tool “elaborates” the first description of the circuit design into a third description for the circuit design. Typically, the third description or “elaboration” will cross one or more hierarchical boundaries represented in the first description of the circuit design, so that the elaboration will represent at least a portion of two or more hierarchical modules in the first description design according to a non-hierarchical or “flat” manner. Also, with some implementations of the invention, the elaboration may include only a simple representation of a corresponding portion of the circuit design.