RTL Connectivity Propagation for SOC Abstraction
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Solution Overview
Problem
Complex System-on-Chip (SOC) designs with millions of transistors pose challenges in reusing existing designs due to poor documentation and low register transfer level (RTL) descriptions, making it difficult for design teams to understand and modify them, especially when original designers are no longer available.
Innovation Solution
A system and method for automatically analyzing and modifying RTL-level netlists to produce higher-level descriptions by propagating signal names and properties across IP block instances based on connectivity, grouping signals, and assigning them to higher-level interface definitions, facilitating a more understandable and manageable design representation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If the design is documented at a detailed RTL level with individual signal names, then the design provides complete technical information, but the complexity of understanding and modifying the design increases significantly
Solution Approach 1:
The patent segments the detailed RTL signal names into higher-level abstraction groups by propagating connectivity information through the design hierarchy. This divides the complex signal naming into manageable segments that can be understood at higher abstraction levels while preserving the complete technical information through the propagation process.
Solution Approach 2:
The patent introduces a new dimension of abstraction by propagating signal names and properties from detailed RTL level up through multiple hierarchy levels to higher-level interface definitions. This dimensional transition allows the same information to be viewed at different levels of abstraction, reducing complexity while maintaining completeness.
2Device complexity
If the design exists only at low RTL description level, then the design is easier to represent, but understanding the design becomes difficult without original designers available
Solution Approach 1:
The patent performs preliminary action by automatically propagating signal names and properties through the design hierarchy before the design needs to be understood or modified. This pre-processing creates higher-level descriptions that are easier to understand, preparing the design for future maintenance without requiring original designers.
Solution Approach 2:
The patent creates a copy of the design information at multiple abstraction levels by propagating connectivity information. This copy preserves the detailed RTL information while presenting it at higher levels of abstraction, enabling understanding without requiring access to the original detailed documentation or designers.
3Measurement precision
If signal names are propagated across all IP block instances, then higher-level descriptions become more accurate, but the processing time and computational resources increase
Solution Approach 1:
The patent applies dynamics by making the propagation process configurable and adaptive. The system can dynamically adjust the scope and depth of propagation based on design needs, allowing high precision when required while reducing processing time for less critical analyses through flexible configuration of propagation parameters.
Data Source
AI summary
A system and several methods for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs, is provided. In particular, interface matching based on connectivity propagation is automatically performed whereby port names and properties on instances of functional elements and blocks are propagated to top level design ports as well as other instances of functional elements and blocks to create a more robust description of connectivity according to the RTL netlist, and to automatically form signal groupings that comprise a higher-level abstracted description. Also, a facility is included to allow user-guided grouping of instantiated interfaces with respect to actual signal names and properties in an RTL-level design.