RTL Design Conversion via Variable Memory Categorization
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Solution Overview
Problem
The design of hardware, such as Application-Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs), is time-consuming and expensive due to the complexity and size of designs, with conventional Register Transfer Level (RTL) design flows being inefficient and costly, particularly in design verification processes.
Innovation Solution
A method and system that converts program code into hardware by categorizing variables as using either implicit or custom memory, defining specific accessor functions for each, and implementing these in a Hardware Description Language (HDL) synthesizable design to generate hardware, allowing for faster verification and implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RTL design flow is used for hardware design, then design verification can be performed, but the verification time and cost increase significantly due to design size and complexity
Solution Approach 1:
The patent creates a software model that replicates the behavior of the hardware design, allowing verification to be performed on the software model instead of the actual hardware. This copying approach enables faster verification cycles while maintaining verification thoroughness, directly addressing the time cost issue in conventional RTL verification
Solution Approach 2:
The patent replaces the mechanical RTL simulation process with a software-based verification model. By substituting the traditional hardware simulation mechanism with a software execution model, the system achieves significantly faster verification times while maintaining verification effectiveness
2Ease of manufacture
If conventional RTL design flow is used for hardware design, then hardware can be implemented, but the design cycle time and cost increase
Solution Approach 1:
The patent performs preliminary verification and validation using the software model before proceeding to actual hardware implementation. This preliminary action identifies and resolves design issues early in the design cycle, preventing costly rework later and reducing overall design cycle time
Solution Approach 2:
By creating and verifying a software copy of the hardware design, the patent enables parallel development and testing activities. This copying approach allows multiple verification scenarios to be executed rapidly on the software model, reducing the sequential design cycle time
3Reliability
If RTL simulation is used for design verification, then verification can be performed, but it becomes too costly and time-consuming for large and complex designs
Solution Approach 1:
The patent creates a simplified software model that captures the essential behavior of the complex hardware design without requiring full RTL simulation. This copying approach maintains verification reliability for critical functions while reducing the computational burden proportional to the design's complexity
Solution Approach 2:
The patent extracts and separates the critical verification functions from the complete hardware design, focusing verification efforts on the most important and complex subsystems. This extraction approach reduces the effective verification complexity while maintaining reliability for the most critical design aspects
Data Source
AI summary
A method for converting a C-type programming language program to a hardware design, where the said program is an algorithmic representation of one or more processes. The C-type programming language program is compiled into a hardware description language (HDL) synthesizable design. The compiler categorizes variables as using either implicit memory or custom memory. Different accessor functions are used depending on which type of memory is used. The programming language may use ANSI C and the HDL may be Verilog Register Transfer Level (RTL). The hardware device generated from the HDL synthesizable design may be an Application-Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA).