RTL Design Checking for Simulation and Synthesis Mismatches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current verification software fails to detect design intent mismatches and simulation/synthesis mismatches in register-transfer level (RTL) designs, leading to misleading equivalence checks between derived and golden designs due to differing tool interpretations and constraints.
Innovation Solution
A system and method for RTL design checking that processes RTL design code to generate an internal representation, compares it with design violation patterns, assigns rule objects, and generates a violation report, including categorization of design patterns into simulation/synthesis mismatches and design intent mismatches, and updates the database with new patterns to improve detection and reporting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification software performs equivalence checks between derived and golden RTL designs, then logical equivalence can be confirmed, but design intent mismatches and simulation/synthesis mismatches cannot be detected due to differing tool interpretations and constraints
Solution Approach 1:
The patent segments the verification process into multiple independent analysis components: syntax analysis, semantic analysis, and equivalence checking. Each component handles specific aspects of RTL design verification separately, allowing design intent mismatches to be detected through semantic analysis while maintaining equivalence check functionality. This segmentation enables the system to identify mismatches that would otherwise be lost in traditional unified verification approaches.
Solution Approach 2:
The patent introduces an intermediary semantic analysis layer between the RTL design input and the equivalence check process. This intermediary analyzes the semantic meaning of RTL code constructs, identifies design intent mismatches, and provides additional verification information that complements the equivalence check results. The semantic analysis acts as a mediator that detects issues before they propagate through the synthesis and simulation tools.
2Reliability
If simulation tools are used to verify RTL designs, then simulation functionality can be confirmed, but verification coverage remains low and simulation/synthesis mismatches are undetected due to shared assumptions and constraints
Solution Approach 1:
The patent performs preliminary semantic analysis of the RTL design code before simulation and equivalence checking. By analyzing the semantic meaning and identifying potential mismatches in advance, the system prepares verification information that guides subsequent simulation and equivalence check processes. This preliminary action increases verification coverage by highlighting areas that require closer examination during simulation.
Solution Approach 2:
The patent adds a new dimension to verification by introducing semantic analysis that operates independently from traditional simulation and equivalence checking. This semantic dimension analyzes the meaning and intent of RTL constructs, providing verification coverage that complements the functional verification achieved through simulation. The multi-dimensional approach allows detection of mismatches that single-dimension methods miss.
Data Source
AI summary
The present disclosure teaches a system and method for register-transfer level (RTL) design checking for exploring mismatches and ambiguous language semantics that occur during the simulation and synthesis phases of the circuit design. In particular, the present disclosure utilizes identified patterns of design violations that occur as a result of these mismatches to create rule objects. The rule objects are then used to identify circuit design violations relating to mismatches between designer intent and ambiguous language. The rule objects are also categorized into different categories so as aid in the analysis of design rule violations and to identify the major impacts to the design qualities and to provide a confidence level of the overall design quality.