RTL DFT Logic via Hierarchical Reference
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Solution Overview
Problem
Current electronic design automation (EDA) tools face difficulties in debugging and equivalence checking when adding design for test (DFT) logic at the register transfer level (RTL) due to obscured functionality and increased simulation time, as well as complications in port creation and back-annotation when inserting DFT logic at the gate level netlist.
Innovation Solution
The approach involves adding DFT logic at the RTL level by creating a new connection to a hierarchical reference within the existing IC design, which reduces the need for new ports and avoids complex port creation and back-annotation, using a tree structure hierarchy to span across multiple hierarchies and maintain logical boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DFT logic is added at gate level netlist, then testability features are added to IC design, but functionality becomes obscured and debugging becomes more difficult
Solution Approach 1:
The patent applies dimensionality change by transitioning from adding DFT logic at the gate level (lower dimension) to adding it at the RTL level (higher dimension). This allows the DFT logic to be integrated in a way that preserves the functional structure and hierarchy of the original design, making debugging easier while still achieving testability. The hierarchical reference mechanism maintains the original design's functional visibility.
2Reliability
If DFT logic is added at gate level netlist, then testability features are added, but simulation time increases significantly
Solution Approach 1:
The patent applies preliminary action by performing DFT logic insertion at the RTL level before the design is converted to gate level netlist. This early insertion allows the DFT logic to be integrated into the functional model that is used for simulation, avoiding the need for time-consuming netlist simulation. The hierarchical reference mechanism enables this early integration while maintaining accuracy.
3Reliability
If wrapper is inserted to connect DFT logic at RTL, then DFT logic can be integrated, but original design hierarchy is modified and equivalence checking becomes complicated
Solution Approach 1:
The patent introduces a hierarchical reference as an intermediary mechanism that connects the DFT logic to the original design without modifying the original design hierarchy. This intermediary allows the DFT logic to access the functional model while preserving the original hierarchical structure, enabling equivalence checking to remain straightforward by comparing the original design with the modified design against the same reference hierarchy.
Data Source
AI summary
Electronic design automation (EDA) systems, methods, and computer readable media are presented for adding design for test (DFT) logic at register transfer level (RTL) into an integrated circuit (IC) design at RTL. In some embodiments, the DFT logic at RTL includes a port that connects to a hierarchical reference with a hierarchical path in the tree structure hierarchy to a part of the IC design at RTL. Such DFT modification helps to decrease the number of new ports added at this stage, and as a result assists subsequent debugging and back-annotation of RTL.