RTL DFT Insertion with Placement Guidance for IC Area Optimization
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Solution Overview
Problem
Existing IC design tools face challenges with long runtimes and poor quality of results (QoR) due to inefficient integration of design-for-testability (DFT) circuitry, which occupies a significant portion of the IC design area and lacks optimal placement guidance.
Innovation Solution
The approach involves adding DFT logic to the register-transfer-level (RTL) representation prior to synthesis, generating DFT placement guidance, and electrically connecting DFT logic with scan chains, ensuring consistent placement with power intent and improved QoR by using techniques such as anchor points and dummy cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DFT circuitry is integrated into IC design, then testability is improved, but device area is consumed (up to 10% of total area)
Solution Approach 1:
The patent merges DFT logic with functional logic at the RTL level by adding DFT logic to the RTL representation before synthesis. This integration allows the synthesis tool to co-locate DFT and functional logic, reducing overall device area while maintaining testability functionality.
Solution Approach 2:
The patent creates multi-functional register stages that serve both functional operation and scan chain operations. The multiplexer in each register stage can route inputs to either functional logic or scan chain inputs, allowing the same hardware resources to fulfill multiple purposes and reduce area overhead.
2Ease of manufacture
If existing IC design tools are used for DFT integration, then design flow is maintained, but runtime is extended and QoR is degraded
Solution Approach 1:
The patent performs preliminary actions by adding DFT logic to the RTL representation and generating DFT placement guidance before the synthesis process begins. This pre-positioning of DFT logic and pre-generation of placement guidance enables the synthesis tool to efficiently place DFT logic near its targets, significantly reducing synthesis runtime and improving quality of results.
Solution Approach 2:
The patent introduces DFT placement guidance as an intermediary mechanism that mediates between DFT logic and scan chain targets during placement. This guidance system acts as a mediator to direct the placement process, ensuring DFT logic is positioned optimally without requiring extensive runtime optimization iterations.
3Adaptability or versatility
If DFT logic is placed without guidance, then placement flexibility is maintained, but DFT logic clumps near test I/O pins resulting in poor QoR
Solution Approach 1:
The patent applies local quality by providing specific placement guidance for DFT logic based on its functional requirements. Different regions of the design receive different placement guidance - DFT logic is directed toward scan chain targets while avoiding excessive concentration near test I/O pins, creating locally optimized placement quality without sacrificing overall flexibility.
Solution Approach 2:
The patent performs preliminary placement guidance generation that pre-determines optimal placement regions for DFT logic before the actual placement process. This preliminary action establishes placement preferences that guide the placer to distribute DFT logic appropriately across the design, preventing clumping while maintaining flexibility.
Data Source
AI summary
Systems and techniques are described for producing a synthesized IC design that includes design-for-testability (DFT) circuitry. A register-transfer-level (RTL) representation of an IC design can be received, wherein the RTL representation includes functional logic. Next, DFT logic can be added to the RTL representation, and DFT placement guidance for placing the DFT logic can be generated. Synthesis can be performed on the RTL representation to obtain the synthesized IC design, wherein during synthesis, (1) the functional logic and the DFT logic can be placed, wherein the DFT logic is placed based on the DFT placement guidance, (2) scan chains can be inserted and placed, and (3) the DFT logic can be electrically connected with the scan chains.