Formal Fault Detection in RTL Design Models
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Solution Overview
Problem
Current formal property qualification methods for industrial RTL designs are inefficient, with weak coverage notions and long run-times, limiting the acceptance and exploitation of formal property-checking technology in chip design due to the need for checking a large number of fault combinations within tight schedules.
Innovation Solution
A method and system for formal fault detection in an instrumented RTL design model, where a plurality of faults and properties are provided, and a formal property checker determines which faults cause each property to fail, reducing the number of necessary checks by iteratively selecting and activating faults, and using a 1-hot predicate to specify a single activated fault, thereby reducing the number of coverage checks by orders of magnitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional formal property qualification methods are used to check all fault combinations, then comprehensive coverage is achieved, but the run-time becomes excessively long (eight years)
Solution Approach 1:
The patent extracts and eliminates redundant checks by identifying that many fault combinations produce equivalent coverage results. Instead of checking all N*M combinations of N faults and M properties, the method extracts only the essential unique checks needed to determine coverage, dramatically reducing the verification space while maintaining completeness.
Solution Approach 2:
The patent performs preliminary analysis to identify which faults can be detected by which properties before executing the full verification. By pre-computing the detection relationships and organizing faults into equivalence classes, the method prepares the verification structure in advance to avoid redundant runtime checks.
2Loss of time
If the number of fault combinations to be checked is reduced, then run-time is decreased, but coverage measurement accuracy may be compromised
Solution Approach 1:
The patent changes the parameter of verification from checking individual fault-property pairs to checking equivalence classes of faults. By transforming the verification space from N*M individual checks to a reduced set of representative checks based on fault equivalence relationships, the method maintains measurement accuracy while reducing computational burden.
Solution Approach 2:
The patent performs a sufficient but not excessive number of checks by identifying the minimal set of fault combinations that provide complete coverage information. Rather than checking all possible combinations or using random sampling, the method determines the exact number of checks needed to achieve complete coverage measurement.
Data Source
AI summary
A method for formal fault detection in a design model includes providing a plurality of faults which are individually activatable in the design model, and providing a plurality of properties for the design model wherein each property of the plurality of properties is valid if none of the plurality of faults is activated. The method further includes selecting a property of the plurality of properties, and determining, by a formal property checker, whether activation of one fault of the plurality of faults causes the selected property to fail. If the formal property checker finds a particular fault which, when activated, causes the selected property to fail, determining that the selected property is capable to detect the particular fault, and if the formal property checker does not find any particular fault which, when activated, causes the selected property to fail, determining that the selected property is not capable to detect any fault of the plurality of faults.