RTL Flip-Flop Selection for Soft Error FIT Reduction
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Solution Overview
Problem
Current RTL design approaches cannot differentiate between flip-flop (FF) devices with different soft error Failure-In-Time (FIT) rates, leading to undesirably high data failure rates in integrated circuit (IC) designs due to exposure to neutrons and alpha particles.
Innovation Solution
A method and system that identify a preferred logic state for each FF in the IC design, adjusting FFs using modified FF devices or layouts to reduce soft error FIT rates, enabling the selection and differentiation of FFs based on their specific FIT rates during the RTL design phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current RTL design approaches are used, then design simplicity is maintained, but soft error FIT rates remain undesirably high
Solution Approach 1:
The patent changes the parameter of FF selection by introducing FIT rate as a differentiation criterion. The system analyzes RTL code to identify sequential devices and selects FFs based on their specific FIT rates, transforming the design approach from uniform FF selection to parameter-based differentiated selection, thereby reducing soft error rates without significantly increasing design complexity
Solution Approach 2:
The patent segments the FF selection process by differentiating between sequential devices based on their FIT rates. Instead of treating all FFs uniformly, the system divides them into categories based on their error characteristics and selects appropriate FF types for each, enabling targeted reliability improvement while maintaining overall design efficiency
2Reliability
If uniform FF selection is used across all sequential devices, then design efficiency is maintained, but data failure rates increase due to undifferentiated soft error protection
Solution Approach 1:
The patent introduces FIT rate as a key parameter for FF selection, changing the design approach from uniform selection to parameter-driven selection. By analyzing the FIT rates of different sequential devices and selecting FFs accordingly, the system achieves both improved reliability and maintained design efficiency through automated differentiation
3Reliability
If FFs are selected without considering FIT rates, then design costs are reduced, but performance and reliability deteriorate due to higher soft error rates
Solution Approach 1:
The system performs self-service by automatically analyzing the RTL code, identifying sequential devices, and selecting appropriate FFs based on their FIT rates. This automated process eliminates the need for manual FF selection while achieving optimized reliability, thereby managing complexity through automation rather than increasing it
Solution Approach 2:
The system incorporates feedback mechanisms by analyzing the characteristics of sequential devices and using this information to guide FF selection. The automated analysis provides feedback on which FFs are most suitable for specific sequential devices based on FIT rates, enabling intelligent selection that improves reliability without proportionally increasing complexity
Data Source
AI summary
A computer-implemented system and method is provided for reducing failure-in-time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The RTL data includes the one or more sequential devices. The method further comprises identifying a preferred logic state for each sequential device of the one or more sequential devices. The method further comprises adjusting the one or more sequential devices based on the preferred logic state.