RTL Logic Partitioning via Hypergraph Timing Analysis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current FPGA prototyping systems face inefficiencies in logic design partitioning due to time-consuming back-end processing and lack of timing-related information, leading to unreasonable circuit structures and performance degradation.
Innovation Solution
A method and system for logic design partitioning that involves collecting RTL design files, performing syntax analysis, extracting and converting logic model objects, constructing a hypergraph-based data structure, and using a timing-driven advanced partitioning algorithm to obtain partitioned data, incorporating clock domain and operating frequency information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional graph theory algorithms are used for partitioning at the back-end, then partitioning can be performed on gate-level netlists, but the processing time becomes very long and the design cycle is seriously affected
Solution Approach 1:
The patent performs partitioning at the RTL level before gate-level synthesis, rather than at the back-end. By conducting the partitioning operation earlier in the design flow when the design is still at the register transfer level, the method avoids the time-consuming processing of gate-level netlists while maintaining partitioning quality through timing-driven optimization
Solution Approach 2:
The patent segments the design processing by separating the partitioning operation from the traditional back-end gate-level processing. It divides the design flow into distinct stages: RTL-level partitioning using timing information, followed by separate gate-level synthesis. This segmentation allows each stage to be optimized independently, reducing overall processing time
2Device complexity
If traditional partitioning methods are used without timing information, then the processing flow is simpler, but the circuit structure becomes unreasonable and operating performance is degraded
Solution Approach 1:
The patent changes the input parameters for partitioning by incorporating timing information (clock domain information and operating frequency) into the RTL-level partitioning process. Instead of using only structural information from netlists, the method uses timing parameters to guide the partitioning algorithm, ensuring that the resulting circuit structure is optimized for actual operating conditions
Solution Approach 2:
The patent introduces timing information as an intermediary element that mediates between the structural design and the partitioning decision. By using clock domain information and operating frequency as intermediate parameters, the method bridges the gap between structural complexity and functional performance, enabling informed partitioning decisions
3Manufacturing precision
If partitioning is performed at the back-end gate-level, then all logic elements can be processed, but the number of graph nodes is very large requiring extensive tuning and iteration
Solution Approach 1:
The patent performs partitioning preliminarily at the RTL level before the design is converted to gate-level netlists. By completing the partitioning operation earlier when the design representation is more compact and timing information is available, the method avoids the complexity of processing large numbers of gate-level nodes while still achieving comprehensive logic element allocation
Solution Approach 2:
The patent inverts the traditional partitioning approach by performing the operation at the RTL level rather than at the gate level. Instead of starting with detailed gate-level information and working upward, the method starts with the higher-level RTL representation and propagates the partitioning decisions downward through subsequent synthesis stages, reducing processing complexity
Data Source
AI summary
A method for logic design partitioning includes: collecting an RTL design file used for describing a logic circuit; performing syntax analysis processing on the RTL design file; extracting an always object and an assign object from logic model objects, and encapsulating the always object and the assign object, respectively; constructing and generating a hypergraph-based data structure; performing attribute analysis, and obtaining operating frequency information by processing according to clock domain information; associating and storing the clock domain information and the operating frequency information with corresponding nodes; and performing partitioning processing to obtain corresponding partitioned data. By means of the solutions of the present invention, other processing at the back end of the flow is not affected, the partitioning time is reduced and the partitioning efficiency is improved. Meanwhile, the logic content in chip design is partitioned efficiently, reasonably and correctly.