RTL Lint Tool for Equivalence Checker Runtime Reduction
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Solution Overview
Problem
Equivalence checking in digital circuit design is challenging due to the complexity of verifying logical equivalence between Register-Transfer Level (RTL) and optimized gate-level netlists, often resulting in hard verification scenarios where tools fail to converge, particularly with don't care conditions and complex data paths.
Innovation Solution
An RTL lint tool identifies potential trigger conditions and data path elements in the RTL design, performs weight calculations to predict problematic areas, and generates recommendations for reducing verification complexity, allowing for early optimization and constraint setup to prevent downstream equivalence checker aborts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If equivalence checking is performed on complex RTL designs with don't care conditions, then verification completeness is improved, but verification runtime increases significantly
Solution Approach 1:
The patent performs preliminary analysis of the RTL design to identify potential trigger conditions and problematic data paths before equivalence checking begins. By pre-calculating weights and generating recommendations for complex logic cones, the system prepares optimization strategies in advance, preventing runtime issues and reducing overall verification time while maintaining completeness.
2Productivity
If aggressive optimization is applied to RTL designs to meet PPA goals, then manufacturing efficiency is improved, but verification difficulty increases
Solution Approach 1:
The patent implements a feedback mechanism where the analysis tool examines the optimized RTL design, identifies trigger conditions caused by aggressive optimization, and generates recommendations to resolve verification difficulties. This feedback loop allows designers to adjust their optimization strategies while maintaining PPA goals, effectively bridging the gap between manufacturing efficiency and verification ease.
3Measurement precision
If comprehensive analysis of all data paths is performed to identify verification issues, then verification accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent applies local quality by focusing analysis resources on specific problematic areas of the design rather than uniformly analyzing all data paths. By calculating weights for different logic cones and identifying trigger conditions in specific regions, the system achieves high verification accuracy where needed while reducing computational complexity in less critical areas.
Data Source
AI summary
Aspects of the present disclosure relate to improving runtime performance of equivalence checkers by a shift left process that uses an RTL lint tool to identify RTL code that can be a source of verification complexity for the downstream equivalence checker. The RTL code is further compared to a corresponding circuit model to determine a potential gate-level location of the potentially problematic RTL code. A weight can be calculated to represent a level of verification complexity that may be generated by the particular portion of the RTL code. Further, one or more recommendations can be generated by the RTL lint tool to prevent some of the verification complexity for the downstream equivalence checker.