RTL to Netlist Equivalence Mapping for Bug Correction
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Solution Overview
Problem
The existing electronic circuit design process is time- and resource-intensive due to the need for re-synthesis when errors are detected in the register transfer level (RTL) abstraction, as correcting bugs in the RTL level requires mapping RTL wires to their netlist counterparts, which is costly in terms of time and resources.
Innovation Solution
The method involves finding logical equivalence between RTL wires and post-synthesis nets by creating an equivalence representation model, associating netlist terminals with RTL entities, simplifying the designs, and using satisfiability solvers and simulations to determine logical equivalents, thereby avoiding the need for re-synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If re-synthesis is performed to map RTL wires to netlist counterparts for bug correction, then mapping accuracy is improved, but time consumption and resource usage increase significantly
Solution Approach 1:
The patent performs preliminary actions by building an equivalence representation model and establishing wire-to-net mapping relationships before bugs are detected. This preliminary mapping structure allows for direct bug correction without requiring time-consuming re-synthesis operations when errors are found during verification stages.
Solution Approach 2:
The patent creates a copied representation of the design in the form of an equivalence representation model that mirrors the structural relationships between RTL wires and netlist nets. This model serves as a lightweight substitute for full re-synthesis, enabling mapping operations without regenerating the entire netlist.
2Measurement precision
If re-synthesis is performed to implement ECO mapping, then mapping completeness is improved, but resource consumption increases
Solution Approach 1:
The patent extracts only the essential mapping information needed for ECO implementation from the full design, storing it in an equivalence representation model. This extraction approach provides sufficient mapping completeness for bug correction while avoiding the resource-intensive process of performing complete re-synthesis of the entire design.
Solution Approach 2:
The patent creates a copied representation of the design in the form of an equivalence representation model that mirrors the structural relationships between RTL wires and netlist nets. This model serves as a lightweight substitute for full re-synthesis, enabling mapping operations without regenerating the entire netlist.
3Manufacturing precision
If detailed wire-to-net mapping is established for every RTL wire, then bug correction precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the complex mapping problem into manageable components by organizing wire-to-net relationships in a structured equivalence representation model. This segmentation maintains precise tracking of individual wire mappings while avoiding the complexity of a monolithic mapping structure, enabling efficient bug correction through localized operations.
Data Source
AI summary
A method, computer program, and apparatus are described for finding the logical equivalence between register transfer level (RTL) wires and post synthesis nets in a netlist. In some example embodiments, the method includes minimizing nets in a netlist and matching each RTL wire to a netlist net. In some example embodiments, the method also includes determining if an RTL wire is logically equivalent to a netlist net. In some example embodiments, the method also includes determining a new candidate for a net if the RTL wire and associated netlist net are not logically equivalent.