Removable RTL Performance Counters for Accurate IC Emulation
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Solution Overview
Problem
The complexity of integrated circuit (IC) chip development leads to prolonged verification phases, increasing time-to-market and project risks due to inaccuracies in software simulations, which lack detail and are not completely accurate, making it challenging to validate performance and correctness before silicon fabrication.
Innovation Solution
The implementation of temporary and removable soft performance counters during the circuit development process, which are configured to extract statistical data from register transfer level (RTL) emulation, allowing for more accurate debugging and validation without occupying chip space or affecting signal timing, using hardware description languages and field programmable gate arrays (FPGAs for emulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software simulators are used for performance verification, then verification can be performed before silicon fabrication, but the accuracy and detail of performance validation is insufficient
Solution Approach 1:
The patent introduces performance counters as an intermediary component between the design under test and the verification environment. These counters are inserted into the RTL design to capture performance metrics directly from the actual design logic, providing accurate performance data without requiring complex software simulation models. The counters act as mediators that bridge the gap between hardware design and performance verification.
Solution Approach 2:
The patent creates simplified copies of performance monitoring functionality that can be integrated into the RTL design. Instead of using complex software simulators, the invention uses lightweight counter circuits that replicate the essential performance measurement capabilities needed for validation. These counter copies provide accurate performance data while consuming minimal resources.
2Reliability
If permanent performance counters are integrated into the final chip design, then accurate performance monitoring is achieved, but chip area and complexity increase
Solution Approach 1:
The patent extracts the performance counter functionality from the final product design, using it only during the verification phase. The performance counters are temporarily integrated into the RTL design for validation purposes, then removed before silicon fabrication. This extraction approach allows accurate performance monitoring during development without permanently increasing chip area or complexity in the final product.
Solution Approach 2:
The patent changes the temporal parameter of the performance counters, making them transient rather than permanent. The counters are enabled during verification and disabled/removed before fabrication, changing their presence parameter from constant to variable. This allows the system to have performance monitoring capability when needed while eliminating it when not required, avoiding permanent area overhead.
3Reliability
If complex performance counters are used during verification, then comprehensive performance validation is achieved, but verification complexity and time-to-market increase
Solution Approach 1:
The patent segments the performance verification functionality into multiple independent counter modules that can be selectively instantiated and configured. Each counter handles specific performance metrics, allowing comprehensive validation through modular components rather than a single complex system. This segmentation reduces verification complexity by breaking down the overall verification task into manageable, independent units.
Solution Approach 2:
The patent introduces dynamic configurability to the performance counters, allowing their behavior and monitoring parameters to be adjusted during verification. The counters can be dynamically enabled/disabled, configured to monitor different metrics, and adapted to various verification scenarios. This dynamic nature reduces complexity by providing flexibility rather than requiring fixed, overly-complex hardware for all possible verification cases.
Data Source
AI summary
Systems, methods, and other embodiments associated with performance counters are described. In one embodiment, a method includes generating a first register transfer level (RTL) description of an integrated circuit that includes a performance counter. The integrated circuit is emulated in hardware and statistical data is collected with the performance counter. The performance counter is then removed from the integrated circuit.