RTL Power Domain Simulation for State Retention Verification
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Solution Overview
Problem
Existing power optimization techniques in integrated circuit design are typically applied at the physical implementation phase, leading to a gap in the RTL to GDSII implementation and verification flow, where the original RTL design cannot accurately represent power management implementations, necessitating the incorporation of power information early in the design process to ensure proper state retention and verification.
Innovation Solution
A method and system for simulating state retention in a power domain using hierarchical RTL representation, which involves receiving a netlist description and power information specifications, identifying power domains, associating them with power control signals through a power manager logic, and simulating state retention behavior in response to power variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power optimization techniques are applied at the physical implementation phase, then power management can be implemented, but the original RTL design cannot accurately represent power management implementations creating a verification gap
Solution Approach 1:
The patent applies preliminary action by incorporating power domain information and state retention specifications into the RTL design environment before physical implementation. Power domain objects are created and associated with RTL modules early in the design phase, allowing verification of power management behavior at the RTL level rather than waiting until physical implementation.
Solution Approach 2:
The patent introduces power domain objects as intermediaries between the RTL design and physical power management implementation. These power domain objects serve as a bridge that carries power management specifications through the design flow from RTL verification through synthesis to physical implementation, maintaining consistency across all phases.
2Use of energy by moving object
If power management techniques are implemented after circuit synthesis, then power optimization can be achieved, but the design intent cannot be captured in the RTL representation
Solution Approach 1:
The patent performs preliminary action by defining power domain characteristics, state retention requirements, and power control signal associations in the RTL design environment before synthesis. This ensures that power management design intent is captured early and maintained throughout the design flow.
Solution Approach 2:
The patent creates a universal power domain representation that serves multiple functions: it defines power management behavior for verification, guides synthesis tools for power optimization, and specifies physical implementation requirements. The same power domain objects are used across different design phases.
3Reliability
If state retention behavior is not simulated in the RTL environment, then the design flow remains simple, but proper state retention and state loss behavior cannot be verified
Solution Approach 1:
The patent applies self-service by enabling the RTL design environment to automatically simulate state retention behavior using the defined power domain objects and control signals. The simulation framework uses the power domain specifications already present in the design to verify state retention without requiring external verification tools or manual analysis.
Data Source
AI summary
Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.