RTL Power Estimation Using Linear Characterization Formulas
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Solution Overview
Problem
Conventional register transfer level (RTL) power estimation methods become impractical for large logic chips due to large lookup tables and fail to accurately account for diverse operation modes and their frequencies, leading to substantial errors in power consumption estimation.
Innovation Solution
A method that parses all possible condition branches in RTL code to construct a hierarchy tree, selects representative input vector sets based on frequency of occurrence, and uses linear characterization formulas to calculate power modes, providing a more accurate and efficient power estimation by accounting for different operation modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional RTL power estimation methods use lookup tables to account for all input vector combinations, then measurement precision of power consumption can be improved, but device complexity and computational time increase exponentially
Solution Approach 1:
The patent segments the power estimation problem by dividing all input vector combinations into distinct operation modes based on conditional statements in RTL code. Instead of treating all combinations uniformly in a single lookup table, the system creates separate characterization formulas for each operation mode, making the estimation scalable and manageable.
Solution Approach 2:
The patent changes the parameter representation from raw input vectors to operation mode identifiers. By parsing conditional statements and constructing hierarchy trees, the system transforms the estimation problem from dealing with exponential input combinations to dealing with a manageable set of operation modes, each characterized by linear formulas.
2Measurement precision
If conventional methods consider all possible input vector sets, then measurement precision improves, but loss of time increases due to exhaustive analysis
Solution Approach 1:
The patent performs preliminary action by pre-parsing the RTL code to identify all possible condition branches and constructing hierarchy trees before actual power estimation. This preliminary structure organization allows rapid classification of input vectors into operation modes during estimation, avoiding time-consuming exhaustive analysis.
Solution Approach 2:
The patent applies partial action by selecting representative input vector sets for each operation mode rather than analyzing all possible input combinations. This sampling approach maintains estimation accuracy while significantly reducing computational time required for power consumption calculation.
3Adaptability or versatility
If the number of logic gates increases to achieve more complicated chip functionality, then adaptability improves, but use of energy increases
Solution Approach 1:
The patent incorporates feedback mechanisms by calculating power consumption for each operation mode and using these results to provide feedback on the impact of different logic gate configurations. This feedback enables optimization of chip design by identifying high-power consumption operation modes and adjusting logic gate placement or configuration accordingly.
Data Source
AI summary
A method for register transfer level power estimation in chip design includes the steps of: (A) parsing all possible condition branches of conditional statements in a register transfer level code, and establishing power modes inducible by each of the possible condition branches; (B) selecting a plurality of representative input vector sets from input vector sets recorded in the chip specification, and constructing linear characterization formulas corresponding to the power modes based on the selected input vector sets; and (C) calculating power values from the linear characterization formulas that correspond to the power modes, and obtaining an average power consumed by the chip from the calculated power values.