RTL Power Estimation via Standard Cell Subset Partitioning
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Solution Overview
Problem
Accurate estimation of power consumption in register-transfer level (RTL) circuit designs is challenging due to the lack of available power models at higher levels of abstraction, making it difficult to optimize designs before significant resources are invested.
Innovation Solution
The method involves calculating power characteristics of RTL netlists by partitioning standard cells and leaf-level instances into subsets based on path length and attributes, then associating standard cells with leaf-level instances using relative percentages, allowing for the estimation of power consumption without the need for complex synthesis procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If power models of standard cells are connected to RTL designs through cell selection, then power consumption estimation accuracy is improved, but the complexity of the cell selection process increases due to numerous possibilities for implementing complex logic functions
Solution Approach 1:
The invention segments the cell selection process by partitioning standard cells into groups based on shared characteristics (logic function, input count, fanout, etc.). This segmentation reduces the complexity of cell selection by organizing the numerous possibilities into structured categories, while still enabling accurate power consumption estimation through selective association of power models with RTL operators.
Solution Approach 2:
The invention changes parameters by selecting specific characteristics (logic function, number of inputs, fanout) to group standard cells, rather than considering all possible variations. This parameter-based approach simplifies the cell selection process while maintaining sufficient accuracy for power consumption estimation at RTL level.
2Measurement precision
If detailed gate-level netlists are used for power estimation, then power consumption accuracy is improved, but computational burden and memory requirements increase
Solution Approach 1:
The invention introduces an intermediary approach by associating power models of standard cells with RTL operators through cell selection, rather than directly using gate-level netlists or relying on inaccurate high-level models. This intermediary method enables accurate power estimation at RTL level without requiring full gate-level detail, thus reducing computational burden while maintaining accuracy.
Solution Approach 2:
The invention applies partial action by selecting only the necessary standard cell characteristics needed for power estimation (logic function, input count, fanout) rather than analyzing complete gate-level netlists. This partial approach provides sufficient accuracy for power consumption estimation while significantly reducing computational resources and memory requirements.
Data Source
AI summary
Systems and methods are provided for calculating a power characteristic of an integrated circuit design. For each standard cell of a gate-level netlist, a path length and a set of attributes are computed. For each leaf-level instance of a register-transfer level (RTL) netlist, a path length and a set of attributes are computed. The standard cells are partitioned into first subsets, each of the first subsets containing standard cells with a same path length and a same set of attributes. For each first subset, a relative percentage for each type of standard cell included in the first subset is calculated. The leaf-level instances are partitioned into second subsets. For each pair of corresponding first and second subsets, standard cells are associated with the leaf-level instances of the second subset based on the relative percentages. A power characteristic of the RTL netlist is calculated based on the associated standard cells.