RTL Power Off Verification for Digital System Design
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Solution Overview
Problem
The existing digital design verification processes are inefficient and time-consuming, particularly in verifying the operational characteristics of devices with multiple power sources, as they require lengthy simulations to account for power supply and blockage scenarios, leading to increased design time and potential errors.
Innovation Solution
A method and system for verifying the power off effect in digital systems by specifying a device model at the register transfer level (RTL) that includes models for both normal and power-blocked scenarios, using a hardware definition language, with test input and output signal models to simulate and verify the behavior of function blocks under different power conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional verification methods are used to verify power supply and blockage scenarios, then verification completeness is improved, but verification time increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-defining power supply and blockage scenarios in the verification methodology before actual verification execution. The verification environment is pre-configured with multiple power source models (normal power supply, partial power blockage, complete power off) and their corresponding operational characteristics are predetermined. This allows the verification process to systematically cover all power scenarios without requiring lengthy real-time simulations, thus reducing verification time while maintaining completeness.
Solution Approach 2:
The patent segments the verification process into distinct power scenario models: normal power supply mode, partial power blockage mode (where specific power sources are blocked), and complete power off mode. Each segment has its own verification rules and operational characteristics. This segmentation allows the verification system to handle complex power scenarios separately and efficiently, avoiding the need to simulate all possibilities simultaneously, thereby reducing overall verification time.
2Measurement precision
If detailed power scenario modeling is implemented, then verification accuracy is improved, but design complexity increases
Solution Approach 1:
The patent introduces an intermediary verification environment that mediates between the design entity and the verification process. This verification environment includes intermediary components such as power source models, scenario generators, and result analyzers that simplify the verification process. The intermediary layer abstracts the complexity of power scenario modeling, providing standardized interfaces and pre-defined operational characteristics that make verification accurate without requiring the design entity itself to be overly complex.
Solution Approach 2:
The patent creates a universal verification environment that can handle multiple power scenarios through a single integrated framework. The verification system is designed with multi-functionality to accommodate normal operation, partial power blockage, and complete power off scenarios without requiring separate verification methodologies for each case. This universality reduces design complexity by consolidating verification procedures while maintaining high accuracy through comprehensive scenario coverage.
Data Source
AI summary
A method of verifying the power off effect of a design entity of a digital system includes a device model, a test input signal model, and a test output signal model specified in a hardware design language, at a register transfer level (RTL). The device model describes function blocks for performing predetermined functions using a plurality of power sources. The device model includes a model for a case where all of the power sources are supplied and a model for a case where one or more of the power sources are blocked. The test input signal model describes a test input signal to be input to the device model to verify the case where all of the power sources are supplied and the case where one or more of the power sources are blocked. The test output signal model describes a test output signal to be output from the device model in response to the test input signal.