Incremental RTL Segmentation for FPGA Design Verification
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Solution Overview
Problem
The existing chip design verification process is inefficient, requiring repeated full processing of RTL segmentation even with minor design modifications, leading to significant time and resource wastage, and impacting production planning.
Innovation Solution
An incremental segmentation processing method that compares the initial and modified syntax tree structures, identifies different nodes, and optimally allocates them between programmable logic devices, reducing the need for full re-processing by re-dividing only changed devices and integrating them logically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the whole process of RTL segmentation is repeated after any design modification, then the verification correctness is maintained, but the processing time and computing resource consumption increase significantly
Solution Approach 1:
The patent segments the syntax tree into multiple sub-trees based on modification locations, allowing only the affected sub-trees to be re-processed while other sub-trees are reused. This divides the verification process into independent segments that can be handled separately, resolving the contradiction between maintaining full verification correctness and reducing processing time.
Solution Approach 2:
The patent extracts and identifies the specific modified nodes and their affected descendant nodes from the syntax tree, separating them from the unchanged portions. By taking out only the modified segments for re-processing while preserving the rest, the system maintains verification correctness for the entire design while minimizing the time-consuming re-processing workload.
2Manufacturing precision
If the whole process of RTL segmentation is repeated after any design modification, then the segmentation accuracy is maintained, but the computing resource consumption increases significantly
Solution Approach 1:
The patent divides the syntax tree into multiple independent sub-trees based on modification locations, allowing the segmentation algorithm to be applied only to affected segments rather than the entire tree. This maintains segmentation accuracy for modified portions while dramatically reducing computing resource consumption by avoiding redundant segmentation of unchanged portions.
Solution Approach 2:
The patent applies different processing quality levels to different parts of the syntax tree: full re-segmentation is applied only to modified nodes and their affected descendants, while unchanged nodes reuse existing segmentation results. This local quality approach maintains high segmentation accuracy where needed while minimizing overall computing resource consumption.
3Adaptability or versatility
If frequent debugging operations are performed on the design file, then design optimization and error correction are achieved, but the repeated full processing reduces debugging efficiency
Solution Approach 1:
The patent performs preliminary identification of modified nodes and their affected ranges before initiating re-processing. By preliminarily determining which segments need re-processing based on syntax tree comparison, the system avoids unnecessary full re-processing for each debugging operation, thereby maintaining high debugging capability while significantly improving debugging efficiency.
Solution Approach 2:
The patent applies partial re-processing action only to the extent necessary - specifically to modified nodes and their affected descendant nodes - rather than performing excessive full re-processing. This partial action approach maintains the ability to handle any debugging operation while dramatically improving debugging efficiency by minimizing redundant processing.
4Reliability
If the whole process of RTL segmentation is repeated after any design modification, then the netlist integration correctness is maintained, but the overall production timeline is extended
Solution Approach 1:
The patent segments the netlist generation process corresponding to the syntax tree segmentation, allowing netlist integration correctness to be maintained for modified portions while reusing netlist results for unchanged portions. This segmented approach ensures correctness where modifications occurred while shortening the overall production timeline by avoiding redundant netlist generation.
Data Source
AI summary
The present invention relates to the field of segmentation algorithms, and provides an incremental segmentation processing method and apparatus, a computer device, and a storage medium. The specific method includes: obtaining and parsing an initial syntax tree structure of an initial design file and a modified syntax tree structure of a modified design file; obtaining initial running data of the initial design file running in the entire process, and configuring a first programmable logic device; comparing the initial syntax tree structure and the modified syntax tree structure to obtain different nodes therebetween; identifying the first programmable logic device and second programmable logic devices according to the different nodes; and performing calculation to obtain the optimal allocation between nodes in a node position distribution state and the second programmable logic devices, and obtaining an incremental segmentation processing result. By means of the processing solution of the present application, a slightly modified design file can be quickly segmented, thereby saving time and improving efficiency.