RTL Semantic Locking Against Untrusted Foundry Reverse Engineering
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Solution Overview
Problem
The increasing cost of IC manufacturing and the risk of intellectual property theft due to outsourcing to untrusted foundries necessitate a secure method for protecting integrated circuit designs against reverse engineering and unauthorized copying.
Innovation Solution
A system and method for register-transfer level (RTL) locking that obfuscates semantic elements such as constants, operations, and control branches in the RTL design using opaque predicates, ensuring the functionality is only unlocked with a predetermined key, and utilizing a black list to exclude certain elements from locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic locking is applied to protect IC design, then security against reverse engineering is improved, but device complexity increases due to extra gates and key installation requirements
Solution Approach 1:
The locking mechanism is segmented into multiple independent opaque predicates distributed throughout the RTL design. Each predicate represents a small, localized security element rather than a single complex locking structure, allowing the security function to be divided into manageable segments that can be independently verified and applied.
Solution Approach 2:
Opaque predicates serve as intermediary elements between the design functionality and the security mechanism. These predicates act as mediators that embed security checks within the normal data flow and control logic, allowing security to be enforced without requiring separate key installation infrastructure or tamper-proof memory components.
2Reliability
If semantic elements are locked using opaque predicates, then provable security against oracle-less attacks is achieved, but manufacturing cost increases due to additional logic gates
Solution Approach 1:
The security strength is adjusted by changing parameters such as the number of opaque predicates, their placement density, and the complexity of individual predicates. This allows optimization of the balance between security level and area overhead, enabling manufacturers to select appropriate security configurations based on cost constraints and threat models.
Solution Approach 2:
Instead of applying locking to every possible semantic element, the method selectively applies opaque predicates to critical portions of the design. This partial action approach provides sufficient security against oracle-less attacks while minimizing the area overhead and manufacturing cost by avoiding excessive locking in non-critical regions.
3Object-affected harmful factors
If RTL design is obfuscated, then resistance to reverse engineering is improved, but verification difficulty increases due to indistinguishable obfuscated circuits
Solution Approach 1:
The verification process incorporates feedback mechanisms where the obfuscated RTL is synthesized to gate-level, and the resulting netlist is analyzed to verify that opaque predicates are properly formed and distributed. This feedback loop ensures that obfuscation does not introduce functional errors while maintaining security, allowing verification despite the indistinguishable nature of obfuscated circuits.
Solution Approach 2:
Traditional manual verification methods are replaced with automated formal verification and synthesis-based checking. The verification system substitutes mechanical/manual inspection with algorithmic analysis that can handle the complexity of obfuscated circuits, using formal methods to prove equivalence between original and obfuscated designs at the behavioral level.
Data Source
AI summary
Exemplary system, method, and computer-accessible medium for protecting at least one integrated circuit (IC) design, includes generating an abstract syntax tree (“AST”) based on a hardware description language and a first register-transfer level (RTL) design. The method also includes selecting semantic elements in the AST to lock and locking the selected semantic elements. Additionally, the method includes a procedure for generating a second RTL design.