RTL Signal Visibility in FPGA Prototyping Systems
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Solution Overview
Problem
Current emulation and prototyping systems for debugging RTL designs have limited visibility due to the hierarchical nature of signal names, which complicates the synthesizing and fitting process, and often require costly and error-prone turn-key systems.
Innovation Solution
Instrumenting the RTL design with dummy modules to correlate signals with gate-level signals, allowing for the extraction of runtime values from the emulation system, including the use of latches to ensure readable signal values at registers or memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If hierarchical signal names are used in RTL design, then signal organization and readability are improved, but synthesizing and fitting process efficiency deteriorates
Solution Approach 1:
The patent segments the signal name hierarchy into two separate representations: the original hierarchical RTL signal names are preserved for readability and organization, while flattened signal names are generated for efficient synthesizing and fitting. The system maintains both representations and maps them to each other, allowing the hierarchical names to remain intact while using flattened versions during the synthesis process to improve productivity.
2Ease of manufacture
If gate-level signal names are used after synthesis, then synthesizing and fitting process is simplified, but signal traceability and debugging capability deteriorate
Solution Approach 1:
The patent introduces an intermediary mapping mechanism that connects hierarchical RTL signal names with flattened gate-level signal names. This mapping preserves the traceability between the original RTL signals and their corresponding gate-level implementations, allowing debuggers to navigate from either representation. The intermediary mapping layer ensures that neither signal name format is lost, maintaining both synthesis efficiency and debugging capability.
Solution Approach 2:
The patent creates a copy of the signal name hierarchy information that is preserved alongside the flattened gate-level signal names. This copied hierarchical information is maintained through the synthesis and fitting processes, allowing the system to reference original RTL signal names even when working with flattened gate-level signals. The copying mechanism ensures that signal traceability is preserved without affecting the simplicity of the synthesizing process.
3Use of energy by moving object
If limited number of signals are captured in emulation systems, then system resource consumption is reduced, but debugging visibility and completeness deteriorate
Solution Approach 1:
The patent applies partial action by selectively capturing and monitoring only the essential signals that are mapped from the RTL design through the instrumentation process. Rather than capturing all possible signals, the system identifies and monitors the critical signals that correspond to important RTL signals, achieving sufficient debugging visibility while minimizing resource consumption. The partial action approach allows the system to focus resources on the most relevant signals for debugging purposes.
Data Source
AI summary
User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.