RTL Simulation Multi-Cycle Path Timing Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Register transfer level (RTL) simulation fails to accurately account for multi-cycle paths, leading to incorrect simulation results and potential design bugs, which are often detected late in the design cycle during gate-level simulation, causing costly iterations and potential re-spins.
Innovation Solution
The method involves accessing an RTL file and a sideband file to identify and modify multi-cycle paths by duplicating portions of these paths, inserting delays, and cutting the original paths from their sources, allowing for accurate simulation of multi-cycle path information during RTL simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If RTL simulation uses zero delay for all combinational paths, then simulation speed is improved, but accuracy of multi-cycle path timing is worsened
Solution Approach 1:
The patent segments the combinational logic into single-cycle paths and multi-cycle paths by inserting dummy registers at specific locations. This segmentation allows the simulation to treat different path types differently - single-cycle paths maintain zero delay for speed, while multi-cycle paths include appropriate delays through the dummy register mechanism, thus resolving the contradiction between simulation speed and timing accuracy.
Solution Approach 2:
The patent introduces dummy registers as intermediary elements between source and destination registers for multi-cycle paths. These dummy registers act as mediators that enforce the required multi-cycle delays without affecting the overall simulation performance. The dummy registers create the necessary timing constraints while allowing the rest of the design to simulate at full speed.
2Measurement precision
If gate-level simulation is used to detect multi-cycle path bugs, then detection accuracy is improved, but time cost and complexity increase
Solution Approach 1:
The patent performs preliminary action by transforming the RTL design into an enhanced version with dummy registers inserted at strategic locations before simulation. This preliminary modification enables RTL simulation to detect multi-cycle path bugs with gate-level accuracy, eliminating the need to wait until gate-level simulation and avoiding costly iterations and re-spins.
Solution Approach 2:
The patent creates a modified copy of the RTL design by duplicating the design and inserting dummy registers in the copied version. This copy allows for accurate multi-cycle path timing analysis without affecting the original design, enabling bug detection at RTL level with the same accuracy as gate-level simulation but with significantly reduced time and complexity.
3Measurement precision
If multi-cycle path delays are inserted in RTL simulation, then timing accuracy is improved, but simulation complexity increases
Solution Approach 1:
The patent applies local quality by inserting dummy registers only at specific locations where multi-cycle paths are identified, rather than modifying the entire design uniformly. This localized approach maintains timing accuracy for multi-cycle paths while keeping the rest of the simulation model simple and unchanged, thus improving timing accuracy without proportionally increasing overall simulation complexity.
Data Source
AI summary
An enhanced RTL simulation including information regarding multi-cycle paths is provided. The multi-cycle path information, which is available in the design constraint file, can be used for timing analysis during RTL simulation. This information can advantageously augment the RTL simulation engine to approximate the cycle delays at the destination registers, thereby providing a more realistic approximation of circuit behavior at the RTL level. Notably, RTL simulation is orders of magnitude faster than gate level simulation. Moreover, design bugs associated with multi-cycle paths are more easily corrected during RTL simulation compared to waiting until the gate level simulation.