RTL Timing Debug via VHDL Code Mapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of microprocessor and SoC designs has increased resource consumption in design verification, leading to longer times for resolving issues in the design cycle, particularly in post-silicon hardware debugging, which is time-consuming and inefficient.
Innovation Solution
A system and method that utilize a cloud-native EDA platform for collaborative hardware logic design and debug, tracing back VHDL code lines to identify timing issues by navigating through PD-VHDL, NHVDL, and SVHDL code lines to pinpoint the responsible code lines, providing additional information for debugging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional post-silicon hardware debugging methods are used, then debugging can be performed on actual hardware, but the process is time-consuming and inefficient
Solution Approach 1:
The system performs preliminary actions by creating and maintaining a mapping database during the pre-silicon verification stage, storing the relationships between test case identifiers, stimulus identifiers, RTL code lines, and physical design code lines. This preliminary preparation enables rapid debugging during post-silicon testing without requiring time-consuming manual tracebacks, directly resolving the contradiction between debugging accuracy and debugging time.
2Reliability
If comprehensive test cases are run to verify design functionality, then design verification coverage is improved, but the time and resources required for testing increase
Solution Approach 1:
The system creates a virtual copy of the design verification environment by maintaining a mapping database that replicates the relationships between RTL code, physical design code, and test case data. This virtual model allows engineers to perform debugging and analysis operations on the copied data structure without requiring access to the actual hardware or re-running comprehensive test suites, thereby maintaining verification coverage while significantly reducing design cycle time.
3Measurement precision
If manual tracing of code lines is performed to identify timing issues, then detailed information can be obtained, but the complexity and time required for analysis increases
Solution Approach 1:
The system implements self-service by automatically performing the complex task of tracing and mapping code lines through the mapping database. When a timing issue is detected during post-silicon testing, the system automatically queries the database using the test case identifier and stimulus identifier to retrieve the corresponding RTL and physical design code lines, eliminating the need for manual tracing and reducing both the complexity and time of the debugging process while maintaining precise issue identification.
Data Source
AI summary
A method, programming product, and/or system is disclosed for identifying flaws in integrated circuits, e.g., processors, that includes: selecting from a list of a plurality of timing issues in an integrated circuit, where each timing issue on the list is represented by one or more VHDL code lines, a particular timing issue to investigate; tracing back the selected one or more VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more selected physical design VHDL (PD-VHDL) code lines; logically navigating across the one or more selected PD-VHDL code lines to one or more corresponding normalized VHDL (NVDHL) code lines; and tracing back the one or more corresponding NHVDL code lines to one or more short-hand VHDL (SVHDL) code lines to identify one or more code lines, written by a code designer, responsible for the particular timing issue being investigated.