RTL Transformation for Low Power Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Low power circuit designs face challenges in ensuring proper functionality due to the lack of power information in RTL descriptions, leading to failures in sequential equivalence checking and preventing the inclusion of power-saving features that could introduce errors.
Innovation Solution
The solution involves transforming RTL circuit models to include power intent descriptions, designating retention and non-retention flops, and performing x-propagation analysis to ensure that unknown binary values are not propagated, allowing for the conversion of retention flops to non-retention flops without introducing errors, and verifying functional equivalence considering power settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power domains are used to reduce power consumption in circuit designs, then energy efficiency is improved, but verification reliability deteriorates because RTL descriptions lack power information causing sequential equivalence checking to fail
Solution Approach 1:
The patent introduces an intermediary power information model that bridges the gap between power domain implementations and RTL verification. This model includes power domain definitions, retention flop specifications, and power state transitions, allowing verification tools to understand power-related behaviors without modifying the original RTL descriptions. The intermediary enables sequential equivalence checking to account for power states while maintaining the original design intent.
Solution Approach 2:
The patent performs preliminary analysis to identify retention flops and power domain boundaries before conducting sequential equivalence checking. By pre-processing the design to extract power information and generate augmented verification models, the system prepares the verification environment in advance, allowing standard verification tools to correctly handle power-domain-specific designs without encountering unexpected failures during the actual equivalence checking process.
2Reliability
If retention flops are used to maintain state during power-off periods, then functionality reliability is improved, but device complexity increases due to additional flops required for state retention
Solution Approach 1:
The patent segments flops into two distinct categories: retention flops that maintain their state during power-off periods and non-retention flops that do not. This segmentation allows the verification process to precisely track which flops require state preservation and which can be reset, enabling more efficient power management strategies without requiring all flops to be retention-type flops. The segmentation reduces unnecessary complexity by applying retention functionality only where absolutely required.
Solution Approach 2:
The patent applies retention functionality locally to specific flops within power domains rather than globally to all flops in the design. By identifying and designating only those flops that actually need to retain state during power-off periods, the system achieves the necessary reliability without the overhead of making every flop a retention flop. This local application of quality optimizes the balance between reliability and complexity.
Data Source
AI summary
A register transfer level (RTL) design is received which models a digital circuit in terms of the flow of digital signals. A power intent description is received which may include a description of power domains, identification of retention flops for each power domain, a list of isolation signals, and power switch definitions. A transformed RTL is produced accounting for functionality described in the power intent description. The transformed RTL includes flops designated as retention flops and non-retention flops. A retention flop module analyzes the flops to ensure that flops are properly designated as retention or non-retention flops. A verification module performs power aware sequential equivalence checking on various RTL and power intent descriptions to verify that RTL and power intent description outputs behave the same when accounting for power states.