RTL Vector Mapping for EDA Power Analysis
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Solution Overview
Problem
Existing electronic design automation (EDA) tools require external mapping files for mapping register-transfer-level (RTL) vector names to gate-level netlist names, which are time-consuming to generate and often need manual modification, limiting the efficiency of vector-based power analysis.
Innovation Solution
A computer-implemented method and system that automatically map RTL vector files to electronic designs by preparing gate objects with transformations to match RTL names, identifying matches without relying on external mapping files or RTL netlists, and writing validation files for mapped and unmapped information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If external mapping files are used for mapping RTL vector names to gate-level netlist names, then mapping coverage can be improved, but the process requires many days to generate and needs several machines
Solution Approach 1:
The patent extracts and eliminates the dependency on external mapping files by implementing automatic name matching algorithms that directly compare RTL vector names with gate-level netlist names using transformation rules, thereby removing the time-consuming file generation process while maintaining mapping coverage
Solution Approach 2:
The system performs self-service by automatically generating the mapping through algorithmic name matching and transformation rules without requiring external tools or manual intervention, enabling the mapping process to be completed quickly using existing design data
2Manufacturing precision
If external mapping files are used for mapping RTL vector names to gate-level netlist names, then mapping coverage can be improved, but manual modification is often required
Solution Approach 1:
The system automatically generates complete mapping files through algorithmic name matching and transformation rules without requiring manual modification, making the process fully automated and eliminating the need for operational intervention while achieving comprehensive mapping coverage
Solution Approach 2:
The patent applies various name transformation rules and parameters (such as removing hierarchical separators, applying custom rules, and transforming name formats) to automatically achieve accurate name matching between RTL and gate-level domains without manual adjustment
3Manufacturing precision
If mapping files are generated using traditional tools, then comprehensive mapping can be achieved, but several machines are required
Solution Approach 1:
The patent extracts and removes the requirement for multiple machines by implementing a streamlined algorithmic approach that processes mapping data using only the available gate-level netlist and RTL vector information, achieving complete mapping with minimal system resources
Solution Approach 2:
The system creates a virtual mapping representation through algorithmic transformation rules that copies and transforms name information directly from existing design files, eliminating the need for external tools and multiple machines while maintaining mapping completeness
4Productivity
If automatic name matching is implemented without external mapping files, then processing speed is improved, but mapping coverage may be reduced
Solution Approach 1:
The patent applies multiple name transformation rules and parameters (such as removing hierarchical separators, applying custom rules, and transforming name formats) to automatically achieve accurate name matching between RTL and gate-level domains, maintaining comprehensive mapping coverage while enabling fast processing
Solution Approach 2:
The system implements a universal name matching framework that handles various naming conventions and transformations through a single automated process, achieving both high processing speed and comprehensive mapping coverage across different design scenarios
Data Source
AI summary
The present disclosure relates to a system and method for mapping an RTL vector file to an electronic design. Embodiments may include receiving, at one or more computing devices, an electronic design at an electronic design automation application and reading at least one gate-level netlist associated with the electronic design. Embodiments may also include preparing each gate object with different transformations so to match a register-transfer-level name and reading at least one vector object from one or more register-transfer-level vector files. Embodiments may further include attempting to identify at least one match in the gate-level netlist, wherein the at least one match is a match between a register-transfer-level name and a gate name. Embodiments may also include writing a validation file including at least one of mapped information and unmapped information.