RTL Verification Code Repair for ASIC and FPGA Coverage
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Solution Overview
Problem
Existing circuit design verification processes are complex and inefficient, particularly in generating accurate and comprehensive test code for field programmable gate arrays (FPGA) and application-specific integrated circuits (ASIC), due to the complexity of RTL-based designs and the limitations of current electronic design automation (EDA) software.
Innovation Solution
A system utilizing large language models (LLMs) to automatically generate and refine verification code, including simulation unit tests and formal verification assertions, by training on RTL files and specifications, and employing a repair stage to correct errors, with feedback loops for continuous improvement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional EDA software is used to generate verification code, then the verification process can be performed, but the code quality and coverage are insufficient due to the complexity of RTL-based designs
Solution Approach 1:
The patent introduces large language models as an intermediary between the RTL design code and the verification code generation process. The LLMs are trained on extensive datasets including RTL code, verification code, and EDA tool outputs to learn the complex mappings and generate high-quality verification code that traditional EDA software cannot produce alone.
Solution Approach 2:
The patent replaces the traditional mechanical/EDA-based code generation system with an AI-based system using large language models. This substitution enables the system to handle the complexity of RTL designs more effectively by leveraging pattern recognition and generative capabilities of LLMs rather than rule-based EDA tools.
2Manufacturing precision
If manual verification code generation is performed to improve code quality, then accuracy may improve, but the time and resources required increase significantly
Solution Approach 1:
The patent implements a self-service verification code generation system where LLMs automatically generate, test, and refine verification code without requiring manual intervention. The system performs self-correction by identifying and fixing errors in generated code, and continuously improves through feedback loops that reuse learned patterns from successful verification cases.
Solution Approach 2:
The patent performs preliminary training of LLMs on extensive datasets of RTL code and verification code before actual code generation. This preliminary action equips the models with the knowledge and patterns needed to generate high-quality verification code efficiently during production use, avoiding the need for time-consuming manual generation.
3Reliability
If comprehensive test coverage is achieved through traditional methods, then all design scenarios are verified, but the process becomes excessively complex and inefficient
Solution Approach 1:
The patent creates a universal LLM-based system that can handle multiple verification tasks including generating test cases, creating assertions, performing formal verification, and analyzing results. This multi-functional approach replaces multiple specialized tools and processes with a single versatile AI system that maintains comprehensive coverage while improving efficiency.
Solution Approach 2:
The patent implements feedback loops where the LLM system analyzes the results of verification tests and uses this information to improve future code generation. The system learns from successful and unsuccessful verification attempts, adjusting its generation strategies to achieve comprehensive coverage more efficiently over time.
Data Source
AI summary
A system generates verification code for a circuit design, such as a circuit design specified in RTL. An RTL file and specification are parsed to obtain ports, design parameters, and other functionality of the circuit design. The parsed RTL file and specification are processed by an LLM to generate a model including descriptions of the ports, design parameters, basic functionality, end-to-end functionality, corner-case scenarios and error scenarios. The model is processed by an LLM to generate a test plan that is processed by an LLM to generate verification code, such as simulation unit tests or formal verification assertions. The verification code may be revised by an LLM to correct syntax errors, improve performance, generate helper assertions, or generate auxiliary logic.