RTL Verification Hardness Ranking via Machine Learning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for estimating the hardness of properties in formal verification, such as SystemVerilog assertions, are inadequate due to the theoretical upper bound being too rough and ad-hoc heuristics having limited feature sets and low prediction accuracy, making it challenging to schedule properties effectively within computational resource constraints.
Innovation Solution
A machine learning-based approach using a Pair-Wise hardness comparison model that evaluates the relative hardness of properties by analyzing a significant number of feature variables, allowing for scalable and accurate prediction of property difficulty, thereby improving the scheduling of properties for efficient verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If theoretical upper bound estimation is used to predict property hardness, then the estimation can be calculated automatically, but the prediction accuracy is too rough and does not correlate well with empirical hardness
Solution Approach 1:
The patent transforms the hardness estimation from using a single theoretical parameter (variable count in COI) to using multiple empirical parameters including variable counts, clause counts, and actual solving times from light-weight engines. This multi-parameter approach significantly improves prediction accuracy while maintaining automation.
Solution Approach 2:
The system uses feedback from light-weight engine solving results to train and improve the hardness prediction model. By incorporating actual solving times and outcomes into the feature set, the model continuously refines its accuracy based on empirical data rather than relying solely on theoretical bounds.
2Device complexity
If ad-hoc heuristics with limited feature sets are used to estimate property hardness, then the estimation process is simple, but the prediction accuracy is low
Solution Approach 1:
The patent extends the estimation from using only a few hand-crafted features to incorporating dozens of features across multiple dimensions including variable statistics, clause statistics, and solving performance metrics. This dimensional expansion dramatically improves prediction accuracy without making the process overly complex.
Solution Approach 2:
The system creates a universal hardness prediction model that works across different property types and design domains by using a comprehensive feature set that captures various aspects of property difficulty. This multi-functional approach allows accurate prediction for diverse verification scenarios.
3Ease of operation
If properties are solved without hardness ranking, then the verification process is straightforward, but the throughput is reduced due to inefficient scheduling
Solution Approach 1:
The system performs preliminary hardness ranking of properties before the main verification process using light-weight engines and machine learning models. This preliminary action enables optimal scheduling decisions to be made in advance, maximizing throughput without complicating the actual verification operation.
Solution Approach 2:
The hardness ranking system dynamically adapts to different design domains and property types by using machine learning models that learn from training data. This dynamic approach optimizes scheduling for each specific verification task while maintaining ease of operation through automated decision-making.
Data Source
AI summary
A method or apparatus comprising a verification system using a processor to utilize a first set of verification engines to solve easy properties of an integrated circuit design, such as RTL, running a machine-learning algorithm for a hardness ranking analysis on a plurality of properties based on data from the first set of verification engines, and ranking the plurality of properties by a hardness of verification. The method or apparatus further to order the plurality of properties based on the hardness of verification.