RTL Verification Code Generation With LLM Feedback Refinement
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Solution Overview
Problem
The complexity of field programmable gate arrays (FPGA) and application-specific integrated circuits (ASIC) designs, specified using register transfer languages (RTL), poses challenges in verifying circuit designs due to the lack of efficient automated test code generation and error detection methods.
Innovation Solution
A system utilizing large language models (LLM) to generate and refine verification code, including simulation unit tests and formal verification assertions, while correcting errors and improving coverage, through a series of stages that parse, model, and test circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automated test code generation is implemented, then productivity is improved, but manufacturing precision deteriorates due to lack of error detection
Solution Approach 1:
The system implements feedback mechanisms where the LLM analyzes verification results and error logs, then uses this information to iteratively improve subsequent test code generation, thereby maintaining both high productivity and improving precision over time
Solution Approach 2:
The LLM acts as an intermediary between the automated code generation system and the verification process, analyzing generated code for potential errors and refining the test code to balance automation efficiency with verification accuracy
2Reliability
If comprehensive verification testing is performed, then reliability is improved, but loss of time increases due to manual code writing
Solution Approach 1:
The LLM performs preliminary analysis of the circuit design and pre-generates verification code frameworks before formal testing begins, identifying potential verification needs and preparing test structures in advance to reduce overall verification time
Solution Approach 2:
The system enables self-service verification where the LLM automatically generates, analyzes, and refines verification code without requiring manual intervention at each step, allowing comprehensive testing to be performed autonomously and efficiently
3Measurement precision
If manual verification code writing is used, then measurement precision is improved, but productivity deteriorates
Solution Approach 1:
The LLM serves as an intelligent intermediary that combines automated generation speed with human-level verification expertise, analyzing and refining generated code to achieve both high productivity and measurement precision
Solution Approach 2:
The system replaces manual mechanical code writing with LLM-based intelligent generation and analysis, using advanced language modeling to substitute human expertise while maintaining or improving both speed and accuracy
Data Source
AI summary
A system generates verification code for a circuit design, such as a circuit design specified in RTL. An RTL file and specification are parsed to obtain ports, design parameters, and other functionality of the circuit design. The parsed RTL file and specification are processed by an LLM to generate a model including descriptions of the ports, design parameters, basic functionality, end-to-end functionality, corner-case scenarios and error scenarios. The model is processed by an LLM to generate a test plan that is processed by an LLM to generate verification code, such as simulation unit tests or formal verification assertions. The verification code may be revised by an LLM to correct syntax errors, improve performance, generate helper assertions, or generate auxiliary logic.