RTL Wire Capacitance Estimation Using Precomputed Parasitic Models
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Solution Overview
Problem
Accurate power estimation at the Register-Transfer Level (RTL) stage of integrated circuit design is challenging due to the lack of available power models, particularly for wire capacitance, which is crucial for optimizing power consumption without performing physical synthesis and placement and routing operations.
Innovation Solution
The system classifies gate-level nets as long or short based on average fanout length and stores them in respective databases, generating parasitic models for each category, allowing for capacitance estimation in RTL circuit designs without physical synthesis, by using a reference post-layout design to apply these models to the RTL circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical synthesis and placement and routing operations are performed to obtain accurate wire capacitance, then measurement precision is improved, but productivity deteriorates due to the time-consuming nature of these operations
Solution Approach 1:
The patent performs physical synthesis, placement, and routing operations in advance on a reference post-layout design to generate pre-computed parasitic models. These models are stored in databases for later reuse during RTL-stage power estimation, eliminating the need to perform time-consuming physical operations during each design iteration
Solution Approach 2:
The patent creates simplified copies of the physical design in the form of parasitic models that capture essential wire capacitance characteristics. These models are stored in long-net and short-net databases and can be quickly applied to RTL designs without requiring the original physical design data, enabling fast estimation while preserving accuracy
2Device complexity
If a single parasitic model is used for all nets, then device complexity is reduced, but measurement precision deteriorates due to the inability to account for different net characteristics
Solution Approach 1:
The patent divides the net population into two distinct segments: long nets and short nets. Each segment is assigned its own dedicated parasitic model stored in separate databases. This segmentation allows the system to account for the different electrical characteristics of long and short nets, improving measurement precision while keeping the complexity manageable through systematic organization
Solution Approach 2:
The patent applies different parasitic models to different net categories based on their specific characteristics. Long nets receive models optimized for their electrical behavior, while short nets receive models tailored to their different characteristics. This local quality approach ensures each net type is modeled with appropriate precision without requiring a single overly complex universal model
Data Source
AI summary
Example systems and methods are disclosed for estimating wire capacitance in an RTL circuit design. In an embodiment, a reference post-layout design is received from a non-transitory storage medium, and gate-level nets within the reference post-layout design are classified as either long nets or short nets based, at least in part, on an average fanout length within the gate-level net. A parasitic model may be generated for each of the gate-level nets, and the gate-level nets and associated parasitic models may be stored within either a long net database or a short net database based on the classification of the gate-level net. A net from the RTL circuit design may be classified as either long or short based, at least in part, on a number of modules crossed by one or more fanouts within the net. If the net from the RTL circuit design is classified as long, then capacitance for the net may be estimated using a parasitic model selected from the long net database. If the net from the RTL circuit design is classified as short, then capacitance for the net may be estimated using a parasitic model selected from the short net database.