RTL X-Propagation Debugging for Logic Circuit Failure Root Cause Identification
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Solution Overview
Problem
In circuit design simulations, identifying the root cause of X-bugs (bugs related to X-values) can be cumbersome and time-consuming, often detected late in the design cycle, leading to increased costs in fixing these issues.
Innovation Solution
A method for debugging logic circuit design simulations by tracing X-values through data paths until they are observed in control paths, and iterating simulations to determine time windows and waveform comparisons to identify the logic block responsible for the failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard HDL simulation semantics are used, then simulation runs smoothly without X-value propagation, but X-bugs remain concealed and undetected
Solution Approach 1:
The patent changes the simulation parameter by enabling X-propagation mode, which alters how X-values are handled in the simulation. This parameter change transforms the simulation behavior from concealing X-bugs to actively propagating and detecting them, allowing bugs to be identified earlier in the design cycle
2Loss of time
If X-propagation is enabled in simulation, then X-bugs can be detected at RTL level, but the process of identifying failure points becomes cumbersome and time-consuming
Solution Approach 1:
The patent introduces an intermediary mechanism that automatically traces X-values through the circuit and generates detailed propagation reports. This intermediary tool bridges the gap between enabling X-propagation and easily identifying failure points, automating the trace process and eliminating the need for manual analysis
Solution Approach 2:
The patent replaces the manual mechanical process of tracing X-values through circuit logic with an automated computational system. The simulator automatically tracks X-value propagation paths, identifies failure points, and generates reports, substituting human effort with algorithmic processing
3Reliability
If gate level simulation is used to uncover X-bugs, then X-bugs are detected, but the process occurs late in the design cycle causing increased fixing costs
Solution Approach 1:
The patent enables X-propagation at the RTL simulation stage, which is performed preliminarily before gate-level simulation. This preliminary action allows X-bugs to be detected and fixed early in the design cycle, preventing them from reaching the more expensive gate-level simulation phase and reducing overall design costs
Data Source
AI summary
Methods for debugging a failure in a logic circuit design simulation by tracing a X-value are provided. In one aspect, a method includes detecting during a X-propagation logic circuit design simulation a failure at a register transfer level of a logic circuit comprising one or more logic blocks and tracing a X-value in a data path of the one or more logic blocks until the X-value is observed in a control path of the one or more logic blocks. The method also includes identifying a logic block comprising a control signal of the control path in which the X-value is observed, and identifying the logic block in which the X-value is observed as a root cause of the failure. Systems and machine-readable media are also provided.