RTOS Context Switching Without Interrupt Disabling
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Solution Overview
Problem
Existing real-time operating systems (RTOS) face data loss issues due to interrupt disabling during context switching, which reintroduces the problem of data loss, especially in systems with high data rates or insufficient peripheral buffering.
Innovation Solution
Implementing an advanced RTOS architecture with an advanced interrupt controller that supports nesting and tail chaining of prioritized interrupts, and redefining context switching to never disable interrupts by using low-priority software interrupts for synchronization primitives handling, ensuring data integrity through a circular buffer or flag-based system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupts are disabled during context switching, then context switching can be performed safely, but data loss occurs from peripherals
Solution Approach 1:
The patent segments the interrupt handling into two parts: a fast interrupt entry that sets a flag and saves minimal state, and a later context switch that processes the interrupt. This allows interrupt flags to be set without disabling interrupts, while context switching still occurs safely by checking flags before switching.
Solution Approach 2:
The patent introduces an intermediary mechanism (interrupt flags and a pending interrupt register) that mediates between the interrupt source and the context switching process. This intermediary allows interrupts to remain enabled while providing a safe mechanism for context switching by checking the pending interrupt state.
2Reliability
If interrupts remain enabled during context switching, then data loss is prevented, but context switching becomes complex and error-prone
Solution Approach 1:
The patent extracts the complex state saving and restoration logic from the context switching process itself and places it in a separate interrupt handler. The context switch only needs to check the pending interrupt register and jump to the appropriate handler, significantly simplifying the context switching logic while maintaining data integrity.
Solution Approach 2:
The patent performs preliminary actions by having interrupt handlers set flags and save essential state information before the context switch occurs. This preliminary preparation allows the context switch to proceed safely without complex state management, as the necessary information is already prepared in advance.
3Speed
If sorted ready lists are used for task scheduling, then highest priority tasks are processed first, but bandwidth is diminished due to sorting overhead
Solution Approach 1:
The patent inverts the traditional approach by using unsorted ready lists instead of sorted ready lists. Instead of maintaining tasks in priority order and selecting the highest priority task, the system uses interrupt flags to indicate which tasks need execution and processes them in the order they are encountered, eliminating the sorting overhead while still ensuring timely processing through the interrupt-driven mechanism.
4Reliability
If the system checks all memory buffers for new data, then no data is lost, but response time for high priority peripherals increases
Solution Approach 1:
The patent uses an intermediary mechanism (peripheral request flags and a pending interrupt register) that allows the system to track which peripherals have data ready without checking all memory buffers. The interrupt-driven architecture ensures that when a peripheral sets its flag, the system will process it promptly through the appropriate interrupt handler, maintaining both data completeness and fast response times.
Data Source
AI summary
The present invention is a novel RTOS/OS architecture that changes the fundamental way that context switching is performed. In all prior operating system implementations, context switching required disabling of interrupts. This opens the possibility that data can be lost. This novel approach consists of a context switching method in which interrupts are never disabled. Two implementations are presented. In the first implementation, the cost is a negligible amount of memory. In the second, the cost is only a minimal impact on the context switching time. This RTOS/OS architecture requires specialized hardware. Concretely, an advanced interrupt controller that supports nesting and tail chaining of prioritized interrupts is needed (e.g. the Nested Vectored Interrupt Controller (NVIC) found on many ARM processors). The novel RTOS/OS architecture redefines how task synchronization primitives such as semaphores and mutexes are released. Whereas previous architectures directly accessed internal structures, this architecture does so indirectly by saving information in shared buffers or setting flags, and then activating a low priority software interrupt that subsequently interprets this data and performs all context switching logic. The software interrupt must be set as the single lowest priority interrupt in the system.