RTP Clock Synchronization Using Baseline Drift Compensation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Clock mismatch between sending and receiving devices in networked environments, particularly in real-time data communications like voice, video, and modem communications, leads to jitter buffer issues and call quality problems due to unsynchronized clocks.

Innovation Solution

The proposed solution involves using the RTP stream to establish a baseline for clock synchronization between sender and receiver, adjusting the baseline based on packet deviations, and using this information to adjust digital PLL or VCO to compensate for drift, ensuring accurate clock calibration without requiring additional protocols.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If internal clocks are used in networked devices, then device independence and flexibility are improved, but clock synchronization between sender and receiver deteriorates

Engineering Contradiction:
Improvedevice independenceVSAvoidclock synchronization
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements feedback by measuring the actual arrival time of packets against expected arrival times based on timestamps, calculating drift, and continuously adjusting the local clock rate to reduce future drift. This closed-loop feedback mechanism maintains synchronization despite independent clocks at each endpoint.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically changes the clock rate parameter of the local device based on measured drift from timestamps in received packets. By adjusting the clock rate up or down, the system compensates for frequency differences and maintains synchronization with the remote device.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If arbitrary buffering and long time-outs are applied, then data loss is prevented, but real-time communication quality deteriorates

Engineering Contradiction:
Improvedata loss preventionVSAvoidcommunication delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent dynamically adjusts the jitter buffer size and time-out parameters based on measured network conditions and clock drift. Rather than using fixed arbitrary values, the system adapts buffering and timing parameters in real-time to balance data loss prevention with minimal delay for voice and video traffic.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If signal processing techniques like Kalman filters are used, then clock drift compensation is improved, but processing complexity and computational requirements worsen

Engineering Contradiction:
Improvedrift detection accuracyVSAvoidprocessing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent uses simple timestamp comparisons and linear drift calculations rather than complex Kalman filters. The approach uses readily available RTP timestamps and basic arithmetic to achieve sufficient synchronization accuracy without requiring sophisticated signal processing algorithms or significant computational resources.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

4Reliability

If IEEE 1588 synchronization is used, then local LAN synchronization is improved, but network scope and protocol dependency worsen

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidnetwork scope
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent makes the existing RTP protocol multi-functional by using its timestamps not only for playback synchronization but also for clock drift measurement and compensation. This eliminates the need for separate synchronization protocols like IEEE 1588 and works across any network type without additional protocol dependencies.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7936794B2Clock management between two end points
Publication Date: 2011.05.03 AVAYA INC
  • US7936794B2 patent drawing
  • US7936794B2 patent drawing
  • US7936794B2 patent drawing

AI summary

Clock correlation can be achieved, for example, utilizing the RTP stream between a sender and receiver by determining a baseline at the start of, for example, a communication. This baseline is derived as a point in time from an arriving packet and represents a point from which subsequent packets deviate. Using this baseline, an early packet or a late packet can be detected. An early packet pushes the baseline down to that earlier point, while late arriving packets, if they are arriving late for a continuous period of time, represents a shift in the opposite direction from the baseline, resulting in a baseline moving to the “earliest” packet out of the sequence of the late arriving packets.