RTS Noise Model for Electronic Circuit Simulation
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Solution Overview
Problem
Semiconductor devices face increased output signal degradation due to random telegraph signal (RTS) noise, particularly in low-power applications, where existing models fail to accurately predict its impact, leading to design and production challenges.
Innovation Solution
Development of an RTS noise model and associated generator to simulate RTS noise in electronic circuit simulations, allowing designers to adjust parameters like voltage, current, and geometry to mitigate noise effects, integrated into a circuit simulator to optimize circuit design and reduce production failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If semiconductor devices are scaled down to smaller sizes, then device integration and power consumption improve, but output signal degradation due to RTS noise increases
Solution Approach 1:
The patent applies preliminary action by performing RTS noise simulation during the circuit design phase using an RTS noise model and generator. This allows designers to predict and mitigate noise effects before actual device fabrication, enabling design modifications that reduce sensitivity to RTS noise while maintaining scaled-down dimensions and low power consumption.
2Ease of operation
If existing standardized transistor models are used, then design process simplicity is maintained, but accuracy in predicting RTS noise impact is insufficient
Solution Approach 1:
The patent introduces an RTS noise model and generator as an intermediary component between the circuit simulator and the transistor model. This intermediary specifically addresses RTS noise effects that are not captured by standardized models, providing accurate noise prediction while maintaining ease of use through automated simulation integration and user-friendly interfaces.
3Object-affected harmful factors
If circuit designs are modified to reduce RTS noise sensitivity, then noise impact decreases, but design complexity and iteration time increase
Solution Approach 1:
The patent performs RTS noise simulation during the initial design phase rather than during later testing or production. This preliminary assessment allows designers to identify and modify noise-sensitive circuits before fabrication, reducing the need for costly and time-consuming post-manufacturing iterations while minimizing overall design cycle time.
Solution Approach 2:
The patent implements feedback by using RTS noise simulation results to guide design modifications. The simulator provides quantitative feedback on noise impact for different design configurations, enabling designers to make informed decisions that reduce noise sensitivity while optimizing for other performance metrics.
Data Source
AI summary
A device may generate, using a random telegraph signal (RTS) noise generator, a simulated RTS noise as input to a transistor included in an electronic circuit. The device may determine, based on the simulated RTS noise input to the transistor, a simulated output signal from the transistor.