RTU CPU Redundancy Synchronization for Warm-Standby Transitions

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Solution Overview

Problem

Synchronizing dual remote terminal unit (RTU) central processing units (CPUs) for transparent data processing in critical infrastructure is challenging, particularly in duplicating events, firmware upgrades, and logic states between warm-standby RTU controllers.

Innovation Solution

A redundancy protocol that enables concurrent synchronization of time-stamped events, firmware upgrades, and logic states between main and standby RTU CPUs using a shared communication channel, ensuring data integrity and seamless transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dual RTU CPUs are used for redundancy, then system availability is improved, but synchronizing data between CPUs becomes complex and difficult

Engineering Contradiction:
Improvesystem availabilityVSAvoidsynchronization complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the synchronization process into distinct types (events, firmware upgrades, logic states) and handles each through specialized protocol mechanisms. Events are segmented into time-stamped records with sequence numbers, firmware updates are segmented into transfer packets, and logic states are segmented into configurable synchronization types. This segmentation allows each data type to be synchronized independently, reducing overall complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary redundancy protocol layer that mediates between the dual RTU CPUs and the underlying communication infrastructure. This protocol layer provides standardized mechanisms for event buffering, firmware transfer coordination, and logic state synchronization, abstracting away the complexity of direct CPU-to-CPU synchronization and providing a unified interface for all synchronization operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If event buffering is implemented on standby RTU CPU, then data loss is prevented during transitions, but memory resources are consumed

Engineering Contradiction:
Improvedata integrityVSAvoidmemory resources
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent implements partial buffering by maintaining event records only for the duration needed to ensure data integrity during transitions. Events are buffered with sequence numbers and timestamps, allowing the standby CPU to reconstruct the event stream without storing all historical events indefinitely. The buffering is excessive only to the extent necessary to cover the transition window, not beyond.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If concurrent synchronization operations are performed on the same communication channel, then communication efficiency is improved, but data conflicts may occur

Engineering Contradiction:
Improvesynchronization efficiencyVSAvoiddata consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent employs preliminary actions to prevent data conflicts before they occur. Sequence numbers are assigned to events before transmission, allowing the receiving CPU to detect and resolve potential conflicts. Firmware upgrade requests are validated and coordinated before transfer begins, ensuring that concurrent operations do not interfere with each other. Logic state synchronization preferences are established in advance to determine which CPU's state takes precedence.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where the receiving CPU acknowledges receipt of synchronized data and reports its current state. This feedback allows the transmitting CPU to verify successful synchronization and adjust its behavior accordingly. The redundancy protocol monitors the status of concurrent operations and provides feedback to coordinate their execution, ensuring data consistency even when multiple synchronization operations are in progress.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12455553B2Remote terminal unit processor redundancy synchronization
Publication Date: 2025.10.28 SCHNEIDER ELECTRIC SYSTEMS USA INC
  • US12455553B2 patent drawing
  • US12455553B2 patent drawing
  • US12455553B2 patent drawing

AI summary

Redundancy synchronization of remote terminal unit (RTU) central processing units (CPUs) associated with an industrial operation includes queuing time-stamped events on a main RTU CPU for transfer to a standby RTU CPU as the time-stamped events are generated on the main RTU CPU (i.e., in real-time). The synchronized RTU CPUs further permit synchronization of logic states and synchronization of firmware upgrades. Synchronization activities occur on the same synchronization communications channel between redundant RTU CPUs.