RTZ-Latch Decision Feedback Equalizer for Low-Delay ISI Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed decision feedback equalizers (DFEs) face challenges in reducing feedback delay and increasing sampling flexibility to effectively mitigate intersymbol interference (ISI) in unified signaling systems, especially as data rates increase and unit interval (UI) time decreases.
Innovation Solution
The use of return to zero (RTZ) latches to provide real-time updates to feedback taps, allowing direct connection to a summing node without intervening logic, enabling low-delay and flexible DFE operation through programmable sampling instances and detection thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DFE techniques are used with master-slave latches, then data bits can be sampled and stored, but feedback delay is increased and sampling flexibility is reduced as data rate increases
Solution Approach 1:
The patent divides the feedback path into two separate latch structures (first and second latches) that operate on different phases of the clock signal. This segmentation allows parallel processing of feedback data, reducing the overall feedback delay while maintaining compatibility with high-speed serial interfaces.
Solution Approach 2:
The patent utilizes periodic clocking with distinct first and second phases to control the latches. By alternating between these phases, the system achieves faster effective feedback rates than a single latch could provide within the same unit interval, thereby reducing feedback delay without increasing complexity.
2Adaptability or versatility
If conventional DFE with fixed sampling is used, then implementation is simple, but sampling flexibility is insufficient for unified signaling that requires both bit-center and bit-edge sampling
Solution Approach 1:
The patent implements dynamic sampling capability by using two latches that can be selectively activated based on the desired sampling point (bit-center or bit-edge). The system can dynamically switch between sampling modes without requiring separate fixed sampling circuits, thereby achieving adaptability while controlling complexity.
Solution Approach 2:
The dual-latch structure serves multiple functions: it provides both bit-center and bit-edge sampling capabilities, supports different unified signaling modes, and maintains backward compatibility with conventional DFE operations. This multi-functionality achieves high adaptability without proportionally increasing device complexity.
Data Source
AI summary
A method and apparatus for advantageously utilizing the reset state of an RTZ shift register to guarantee proper data alignment at the feedback taps to facilitate decision feedback equalization (DFE) in a unified signaling system. An input data stream is sliced into an even data stream and an odd data stream, whereby the sliced data is compared to a programmable threshold depending upon a detection mode. Each bit of the even data stream is propagated through RTZ latches and each bit of the odd data stream is propagated through RTZ latches. At any given instant in time, a correct portion of the RTZ latch outputs contain zero information, so that each latch output may be summed in a current mode without the need for any intervening logic. The input data stream is summed in current mode with the feedback data and converted to voltage prior to sampling the currently received data bit.