Hybrid Ru Interconnect Structure for CMP-Stable Fine Pitch Routing
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Solution Overview
Problem
The formation of interconnect structures in semiconductor devices with high device density and performance requires improved resistance and capacitance (RC) characteristics, which is challenging due to the complexity of metal line and via formation.
Innovation Solution
The implementation of a hybrid interconnect structure that combines a top via process and a damascene process, using ruthenium (Ru) for the metal lines and vias, and incorporating dummy top vias to facilitate chemical-mechanical polishing (CMP) operations and reduce the risk of short-circuit or bridging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hybrid interconnect structure combining top via process and damascene process is implemented, then contact resistance and capacitance are reduced, but process complexity increases
Solution Approach 1:
The interconnect structure is divided into two distinct formation processes: top via process for first vias (M1 to M2 connections) and damascene process for second vias (M2 to M3 connections). This segmentation allows each process to be optimized independently, reducing overall RC while managing complexity through modular fabrication steps
Solution Approach 2:
Different via formation methods are applied to different interconnect levels based on local requirements. First vias use top via process with metal line patterning for better alignment, while second vias use damascene process for improved planarity and CMP control, optimizing each level's electrical and mechanical properties
2Manufacturing precision
If dummy top vias are incorporated to facilitate CMP operations, then CMP stability and uniformity are improved, but device density is reduced
Solution Approach 1:
Dummy top vias serve as intermediary structures during CMP operations. These non-functional vias act as reference points and load distributors that stabilize the polishing process, ensuring uniform removal rates across the wafer surface without affecting final device functionality
Solution Approach 2:
Dummy top vias are formed in advance during the via patterning stage, before CMP operations begin. This preliminary placement of dummy structures prepares the surface for stable CMP processing, preventing dishing and uneven polishing that would occur without these sacrificial elements
3Manufacturing precision
If ruthenium is used for metal lines and vias without connection surfaces or boundaries, then manufacturing precision is improved, but process difficulty increases
Solution Approach 1:
The metal line and via structures are merged into a continuous ruthenium formation process without distinct interfaces or boundary layers. This integration eliminates alignment errors at interfaces and simplifies the stack structure, though it requires precise control of the single-material deposition and patterning processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the connection performance of semiconductor devices by reducing contact resistance and capacitance, while also improving the stability and uniformity of CMP operations, thus addressing the challenges of fine pitch metal line formation and via alignment.
Implementation Method 1
a plurality of 1st metal lines above the transistor structure; and a plurality of 1st vias formed on selected 1st metal lines, respectively, among the plurality of 1st metal lines
Implementation Method 2
incorporating dummy top vias to facilitate chemical-mechanical polishing (CMP) operations
Data Source
AI summary
Provided is a semiconductor device which includes: a transistor structure; a plurality of 1st metal lines above the transistor structure; and a plurality of 1st vias formed on selected 1st metal lines, respectively, among the plurality of 1st metal lines; a 2nd via formed on a 1st via among the plurality of 1st vias; and a 2nd metal line on the 2nd via, wherein the 1st metal lines are arranged in a 1st direction and extended in a 2nd direction which intersects the 1st direction, and the 2nd metal line is extended in the 1st direction, and wherein the plurality of 1st vias comprise at least one dummy via which is not connected to any metal line thereabove other than an underlying 1st metal line among the selected 1st metal lines.