Ru/Mo Via-Wire Stack With Recessed Via Edge for Lower BEOL Resistance

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Solution Overview

Problem

Existing back end of line (BEOL) structures in integrated circuit devices face challenges in reducing resistance and preventing electrical shorts due to high resistance adhesion layers between conductive elements, which also affect time-dependent dielectric breakdown (TDDB) margins.

Innovation Solution

Incorporating ruthenium (Ru) or molybdenum (Mo) for both metal vias and wires without an adhesion layer, and creating a recessed edge portion on the upper surface of the lower via to increase the distance between vias and wires, thereby reducing resistance and preventing electrical shorts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If adhesion layers are used between metal vias and wires, then bonding strength is improved, but resistance increases

Engineering Contradiction:

Improvebonding strengthVSAvoidresistance

Core Design Contradiction:

StrengthVSReliability

Solution Approach 1:

The patent removes the adhesion layer from the conventional structure, eliminating the harmful high-resistance element while maintaining bonding through direct metal-to-metal contact between the via and wire, both made of ruthenium or molybdenum

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses the same material (ruthenium or molybdenum) for both the metal via and metal wire, creating a homogeneous conductive structure that eliminates interface resistance and bonding strength issues associated with material mismatches

Inventive Principle:

Principle #33Homogeneity

2Reliability

If distance between conductive elements is increased, then electrical short prevention is improved, but device area increases

Engineering Contradiction:

Improveelectrical short preventionVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent creates a recessed edge portion on the upper surface of the lower via, utilizing vertical dimensionality to increase the horizontal distance between conductive elements without expanding the overall device footprint, thereby preventing electrical shorts while maintaining compact area

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentEP4270474A1Integrated circuit devices including a via and methods of forming the same

Publication Date: 2023.11.01 SAMSUNG ELECTRONICS CO LTD

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AI summary

Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a lower metal via (15), an upper metal via (25), a lower metal wire (27-1) comprising a lower surface contacting the lower metal via (15) and an upper surface contacting the upper metal via (25), and an upper metal wire (37) on the upper metal via (25). The upper metal via (25) is between the lower metal wire (27-1) and the upper metal wire (37), and each of the lower metal via (15), the lower metal wire (27-1) and the upper metal via (25) comprises ruthenium, Ru, or molybdenum, Mo.