Ru Metallization Planarization Without CMP for Contact Etch Inspection
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Solution Overview
Problem
The challenge of planarizing semiconductor devices with ruthenium (Ru) metallization is difficult due to the hardness of Ru, and existing chemical-mechanical polishing (CMP) techniques are not well established, while copper (Cu) metallization faces challenges in the sub-10 nm regime, necessitating improved metallization and defect inspection methods.
Innovation Solution
A method involving ruthenium metallization that bypasses Ru CMP by using a known CMP process on a common material like silicon oxide, combined with electron beam inspection (EBI) in voltage contrast (VC) mode for defect detection, enabling planarization and defect inspection, particularly for sub-10 nm contact holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical-mechanical polishing (CMP) is used to planarize ruthenium metallization, then surface flatness is improved, but the process becomes difficult and unreliable due to the hardness of Ru
Solution Approach 1:
The patent introduces an intermediary material layer (such as silicon oxide or silicon nitride) deposited over the ruthenium metallization. This intermediary layer serves as a mediator that can be easily planarized using standard CMP processes, while the underlying ruthenium layer remains unaffected by the polishing difficulties. The intermediary layer transfers the planarization function from the Ru surface to a more polishable material surface.
Solution Approach 2:
The patent segments the metallization structure into multiple layers: a ruthenium layer for electrical functionality and an overlying dielectric layer for planarization. This segmentation separates the electrical function (Ru) from the mechanical planarization function (dielectric layer), allowing each layer to be optimized independently for its specific purpose.
2Productivity
If ruthenium metallization is used in sub-10 nm contact holes, then manufacturing capability is improved, but defect detection becomes more difficult
Solution Approach 1:
The patent utilizes electron beam induced voltage contrast imaging, where defects in the ruthenium metallization appear as distinct brightness variations (color changes) in the imaging signal. This contrast mechanism enables detection of sub-10 nm defects by translating electrical property variations into visible intensity differences in the image.
Solution Approach 2:
The patent replaces physical/mechanical inspection methods with electron beam-based voltage contrast imaging. This substitution enables non-contact, high-resolution defect detection that is sensitive to electrical properties of the ruthenium metallization, overcoming the limitations of optical or physical measurement methods at sub-10 nm scales.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective planarization of Ru surfaces without Ru CMP, improves process robustness, and facilitates defect inspection, enhancing tool capability and contact etch process evaluation.
Implementation Method 1
The wafer is polished so that the top surface of the metal material and the top surface of the insulating layer are co-planar. In some embodiments, the polishing includes executing a chemical-mechanical polishing (CMP) process of the insulating layer.
Implementation Method 2
The wafer is characterized by electron beam inspection (EBI) in voltage contrast (VC) mode to determine whether a defect of the etch process exists.
Data Source
AI summary
A method of defect detection includes providing a wafer including an insulating layer formed over a conductive layer. An opening is formed in the insulating layer by an etch process. A metal material is deposited in the opening and then etched to form a recess in the insulating layer so that a top surface of the metal material is below a top surface of the insulating layer. The wafer is polished so that the top surface of the metal material and the top surface of the insulating layer are co-planar. The wafer is characterized by electron beam inspection in voltage contrast mode to determine whether a defect of the etch process exists. The defect exists when a VC signal of the opening is below a threshold, and the defect does not exist when the VC signal of the opening is at or above the threshold.