Ru-Pt Capacitor Electrode Structure to Block Interfacial Oxides
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Solution Overview
Problem
The formation of interfacial oxides such as strontium oxide (SrOx) during the deposition of SrTiO3 on a ruthenium (Ru) lower electrode using atomic layer deposition (ALD) leads to deteriorated dielectric and leakage current properties in capacitors, and the high crystallization temperature required for SrTiO3 formation poses a challenge in miniaturized DRAM devices.
Innovation Solution
A capacitor structure is developed with a platinum ultra-thin film layer laminated on a ruthenium thin film layer, and SrTiO3 is deposited on this platinum layer using area-selective atomic layer deposition, preventing the formation of interfacial oxides and allowing crystallization at low temperatures below 500°C.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SrTiO3 is deposited on ruthenium lower electrode using atomic layer deposition, then high-k dielectric film can be formed, but interfacial oxides (strontium oxide) are generated at the interface
Solution Approach 1:
A platinum ultra-thin film layer is introduced as an intermediary between the ruthenium lower electrode and the SrTiO3 dielectric film. This platinum layer prevents direct interaction between strontium and ruthenium, thereby blocking the formation of interfacial oxides while maintaining the high-k dielectric properties of SrTiO3
Solution Approach 2:
The lower electrode is designed as a composite structure combining ruthenium and platinum ultra-thin film layers. This composite structure leverages the low specific resistance of ruthenium and the oxide-blocking properties of platinum to prevent interfacial oxide formation
2Manufacturing precision
If SrTiO3 is deposited through atomic layer deposition on ruthenium, then thin film with excellent step coverage can be achieved, but capacitor thickness increases and equivalent oxide film thickness deteriorates
Solution Approach 1:
The deposition process parameters are optimized to achieve atomic layer deposition of SrTiO3 with excellent step coverage while controlling film thickness. The platinum layer thickness is precisely controlled at ultra-thin levels to block oxides without significantly increasing overall capacitor thickness
3Stability of the object's composition
If high crystallization temperature is applied for SrTiO3 formation, then crystalline dielectric film can be obtained, but process temperature exceeds 500°C limit for miniaturized DRAM devices
Solution Approach 1:
The platinum ultra-thin film layer acts as a mediator that enables crystalline SrTiO3 formation at lower temperatures by preventing oxygen loss and maintaining stoichiometric composition during deposition, thereby eliminating the need for high-temperature crystallization processes
4Reliability
If ruthenium is used as lower electrode, then low specific resistance and leakage current suppression can be achieved, but oxidation and oxygen scavenging effects occur during SrTiO3 deposition
Solution Approach 1:
The platinum ultra-thin film serves as a protective intermediary that prevents oxygen from reaching the ruthenium layer during SrTiO3 deposition, thereby eliminating oxidation and oxygen scavenging effects while preserving the low leakage current properties of ruthenium
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves dielectric and leakage current properties by blocking interfacial oxides, reduces equivalent oxide film thickness (EOT), and meets the temperature limitations of DRAM processes while maintaining high capacitance.
Implementation Method 1
a lower electrode having a structure in which a platinum ultra-thin film layer is laminated on a ruthenium thin film layer
Implementation Method 2
SrTiO3 is deposited on this platinum layer using area-selective atomic layer deposition
Implementation Method 3
allowing crystallization at low temperatures below 500°C
Data Source
AI summary
The present invention relates to a capacitor and a method for manufacturing the same that can improve a dielectric property and a leakage current property of the capacitor by enabling the deposition of a crystalline dielectric film under a low process temperature of 500° C. or lower simultaneously with fundamentally blocking the generation of interfacial oxides when depositing oxides having a perovskite crystal structure through atomic layer deposition (ALD). The capacitor according to the present invention is characterized by comprising a lower electrode having a structure in which a platinum ultra-thin film layer is laminated on a ruthenium thin film layer; a dielectric film laminated on the platinum ultra-thin film layer; and an upper electrode laminated on the dielectric film.