Rule Compilation for Fast Packet Classification
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Solution Overview
Problem
High-speed packet classification in data networks faces challenges due to the need for flexible and sophisticated rule matching, which is inefficient with existing methods that rely on costly Ternary Content-Addressable Memory (TCAM) and results in performance degradation as the number of hash tables and rule entries increases.
Innovation Solution
The approach clusters Rule Patterns (RPs) into extended Rule Patterns (eRPs) using a processor, minimizing the number of hash tables and rule entries while meeting a collision condition, allowing for efficient packet classification using hash tables in RAM, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If TCAM is used for packet classification, then classification flexibility is improved, but device cost and complexity increase
Solution Approach 1:
The patent replaces expensive TCAM hardware with software-based rule compilation and hashing algorithms running on standard processors. Rule patterns are extracted from TCAM-style rules and compiled into hash tables that can be efficiently queried using standard CPU instructions, achieving TCAM-like functionality through software copying rather than hardware implementation
Solution Approach 2:
The patent substitutes the mechanical/electrical TCAM hardware system with a software-based processing system using standard CPUs and RAM. The classification function is migrated from dedicated hardware (TCAM) to general-purpose computing (processor + memory), reducing hardware complexity and cost while maintaining classification capabilities
2Measurement precision
If the number of hash tables and rule entries increases, then classification precision is improved, but processing speed deteriorates
Solution Approach 1:
The patent merges multiple rule patterns into extended rule patterns (eRPs) that can be represented by fewer hash tables. By clustering similar rule patterns and using bitwise operations to represent multiple patterns simultaneously, the system reduces the total number of hash table lookups required while maintaining comprehensive classification coverage
Solution Approach 2:
The patent transforms the classification approach by changing parameters from individual rule-based hashing to extended rule pattern hashing with bitwise operations. This parameter change enables processing multiple classification rules in parallel through bit manipulation, significantly improving processing speed while maintaining precision
3Reliability
If more rule entries are stored, then classification completeness is improved, but lookup time increases
Solution Approach 1:
The patent performs preliminary compilation of rule patterns into extended rule patterns and pre-computes hash values before actual packet classification. Rule patterns are analyzed, clustered, and transformed into optimized hash table structures in advance, so that during runtime, only fast hash lookups and bitwise comparisons are needed, minimizing lookup time while maintaining completeness
Data Source
AI summary
A classification apparatus includes a memory and a processor. The memory is configured to store rules corresponding to a corpus of rules in respective rule entries, each rule includes a respective set of unmasked bits having corresponding bit values, and at least some of the rules include masked bits. The rules in the corpus conform to respective Rule Patterns (RPs), each RP defining a respective sequence of masked and unmasked bits. The processor is configured to cluster the RPs, using a clustering criterion, into extended Rule Patterns (eRPs) associated with respective hash tables including buckets for storing rule entries. The clustering criterion aims to minimize an overall number of the eRPs while meeting a collision condition that depends on a specified maximal number of rule entries per bucket.