Run-Length-Limited Encoder Packets for Stable Clock Recovery
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Solution Overview
Problem
Existing encoders face challenges in stabilizing clock-data recovery circuits by efficiently encoding signals with varying bit values, leading to potential errors due to excessive run lengths of consecutive bits, which can disrupt data transmission in electronic devices.
Innovation Solution
An encoder method that generates data packets with a controlled maximum run length by determining symbols within bit streams and replacing them with packet symbols, including a header and packet symbols, to maintain a run length equal to or less than a predetermined value, thereby minimizing errors and optimizing encoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the encoder transmits data packets with long consecutive runs of identical bits, then the data transmission can maintain simplicity, but the clock-data recovery circuit becomes unstable and errors increase
Solution Approach 1:
The encoder transforms the bit stream by changing the run-length parameter characteristics. It breaks up long consecutive runs of identical bits by inserting transition bits, thereby changing the statistical parameters of the bit sequence to ensure maximum run length does not exceed a predetermined threshold, stabilizing the clock-data recovery circuit without complex additional hardware
Solution Approach 2:
The encoder acts as an intermediary between the data source and the transmission channel, preprocessing the bit stream by inserting transition bits at strategic positions. This intermediary action modifies the bit sequence to prevent excessive run lengths before transmission, resolving the stability issue without requiring complex changes at the receiver end
2Reliability
If the encoder limits the maximum run length of data packets, then clock-data recovery stability improves, but the encoding process becomes more complex and overhead increases
Solution Approach 1:
The encoder segments the bit stream into units and processes each segment to ensure run length constraints are met. By dividing the continuous bit stream into manageable segments and applying transition bit insertion rules to each segment independently, the encoding complexity is distributed and controlled rather than requiring complex global processing
Solution Approach 2:
The encoder applies partial action by inserting transition bits only where necessary to break up excessive runs, rather than transforming the entire bit stream uniformly. This selective approach limits the run length to meet stability requirements while minimizing the amount of additional processing and overhead introduced
3Reliability
If the encoder inserts transition bits to control run length, then transmission reliability improves, but the data packet size increases and encoding overhead increases
Solution Approach 1:
The encoder inserts transition bits partially, only where necessary to prevent excessive run lengths, rather than uniformly across the entire data packet. This selective insertion minimizes the increase in data packet size while still achieving the reliability goal of stabilizing clock-data recovery
Solution Approach 2:
The encoder changes the run-length parameter distribution by strategically inserting transition bits to ensure no consecutive run exceeds the predetermined maximum. This parameter control achieves reliable transmission with minimal overhead by optimizing the placement of transition bits rather than adding them uniformly
Data Source
AI summary
Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes “M” consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.